From: Jason Ekstrand Date: Thu, 15 Jun 2017 05:27:20 +0000 (-0700) Subject: i965/barrier: Do the correct flushes for texture updates X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45991479a3f83501652240a66424a7b64a93e4d7;p=mesa.git i965/barrier: Do the correct flushes for texture updates Texture uploads and downloads may go through the render pipe which may result in texturing from or rendering to the texture or the PBO. We need to flush accordingly. Reviewed-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 9ec2917c90e..3743fa9b5eb 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -268,8 +268,10 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers) if (barriers & GL_TEXTURE_FETCH_BARRIER_BIT) bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - if (barriers & GL_TEXTURE_UPDATE_BARRIER_BIT) - bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + if (barriers & (GL_TEXTURE_UPDATE_BARRIER_BIT | + GL_PIXEL_BUFFER_BARRIER_BIT)) + bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | + PIPE_CONTROL_RENDER_TARGET_FLUSH); if (barriers & GL_FRAMEBUFFER_BARRIER_BIT) bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |