From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 09:01:02 +0000 (+0100)
Subject: add the subvl offset to sv_insn_t
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=459d950df7eaed79f3bb395f9abeb544dc81f86b;p=riscv-isa-sim.git

add the subvl offset to sv_insn_t
---

diff --git a/id_regs.py b/id_regs.py
index c641c90..04d9163 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -202,9 +202,13 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
 
     res.append('#define PRED_ARGS %s' % ','.join(predargs))
     offsargs = []
+    suboargs = []
     for i in range(len(predargs)):
         offsargs.append(predargs[i].replace('pred', 'offs').replace("&", ''))
     res.append('#define OFFS_ARGS %s' % ','.join(offsargs))
+    for i in range(len(predargs)):
+        suboargs.append(predargs[i].replace('pred', 'subo').replace("&", ''))
+    res.append('#define SUBO_ARGS %s' % ','.join(suboargs))
 
     return '\n'.join(res)
 
@@ -220,6 +224,7 @@ if __name__ == '__main__':
         twin_predication = False
         immed_offset = False
         is_branch = False
+        print regsname
         with open(regsname, "w") as f:
             txt = "\n#define INSN_%s\n" % insn.upper()
             # help identify type of register
diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 7b38593..8f14778 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -30,6 +30,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #define SRC_PREDINT 1
 #define PRED_ARGS dest_pred,dest_pred,dest_pred,dest_pred,dest_pred,&dest_pred
 #define OFFS_ARGS dest_offs,dest_offs,dest_offs,dest_offs,dest_offs,dest_offs
+#define SUBO_ARGS dest_subo,dest_subo,dest_subo,dest_subo,dest_subo,dest_subo
 #else
 #define sv_enabled true
 #endif
@@ -74,7 +75,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
   sv_insn_t insn(p, sv_enabled, bits, floatintmap, xlen,
                  INSN_SRC_FLEN, INSN_DEST_FLEN,
-                 PRED_ARGS, OFFS_ARGS,
+                 PRED_ARGS, OFFS_ARGS, SUBO_ARGS,
 #ifdef INSN_TYPE_SIGNED
                  true
 #else
diff --git a/riscv/sv.cc b/riscv/sv.cc
index ac98c69..99b0f7b 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -50,6 +50,8 @@ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
+            int *s_rd, int *s_rs1, int *s_rs2, int *s_rs3, int *s_sp,
+            int *s_imm,
             bool _sign) :
             insn_t(bits), p(pr), src_bitwidth(0),
             xlen(_xlen), src_flen(_src_flen), dest_flen(_dest_flen),
@@ -59,6 +61,9 @@ sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             offs_sp(o_sp),
             offs_imm(o_imm),
+            subo_rd(s_rd), subo_rs1(s_rs1), subo_rs2(s_rs2), subo_rs3(s_rs3),
+            subo_sp(s_sp),
+            subo_imm(s_imm),
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
             save_branch_addr(0)
 {
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index f1d53fc..1f62ade 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -30,6 +30,7 @@ struct reg_spec_t
 {
     reg_t reg;
     int *offset;
+    int *suboff;
     bool isvec;
     bool signextend;
 };
@@ -43,6 +44,8 @@ public:
             uint64_t &p_sp, uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
             int *o_imm,
+            int *s_rd, int *s_rs1, int *s_rs2, int *s_rs3, int *s_sp,
+            int *s_imm,
             bool _sign);
 
   uint8_t reg_elwidth(reg_t reg, bool intreg);
@@ -138,6 +141,14 @@ private:
   int *offs_rs3;
   int *offs_sp;
   int *offs_imm;
+
+  int *subo_rd;
+  int *subo_rs1;
+  int *subo_rs2;
+  int *subo_rs3;
+  int *subo_sp;
+  int *subo_imm;
+
   uint64_t &prd;
   uint64_t &prs1;
   uint64_t &prs2;