From: lkcl <lkcl@web>
Date: Sun, 7 Mar 2021 16:38:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~70
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45b0721e62db6c053f567ecd7710f72f79f9b0c7;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd/logicops.mdwn b/3d_gpu/architecture/dynamic_simd/logicops.mdwn
index 5262d3b92..48f325b5c 100644
--- a/3d_gpu/architecture/dynamic_simd/logicops.mdwn
+++ b/3d_gpu/architecture/dynamic_simd/logicops.mdwn
@@ -18,12 +18,12 @@ they are instead SIMD versions of:
 
 more specifically (8x8 version):
 
-     result = 0 # 64 bit, clear all bits
+     result = 0 # i bit, clear all bits
      for j in range(8)
          partial = 0 # initial value (single bit)
          for i in range(8):
              partial = partial xor a[i+j*8]
-         result[j*8] = partial
+         result[j] = partial
 
 # Requirements