From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Jul 2014 17:03:57 +0000 (+0200)
Subject: Added "make SMALL=1"
X-Git-Tag: yosys-0.4~448
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45b4154b3799178a432d1f14dcaf51787b86f35d;p=yosys.git

Added "make SMALL=1"
---

diff --git a/Makefile b/Makefile
index e061b9c7a..e4e0287e7 100644
--- a/Makefile
+++ b/Makefile
@@ -22,6 +22,7 @@ EXTRA_TARGETS =
 TARGETS = yosys yosys-config
 
 PRETTY = 1
+SMALL = 0
 
 all: top-all
 
@@ -124,6 +125,9 @@ OBJS += libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/
 OBJS += libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o
 
 OBJS += libs/sha1/sha1.o
+
+ifneq ($(SMALL),1)
+
 OBJS += libs/subcircuit/subcircuit.o
 
 OBJS += libs/ezsat/ezsat.o
@@ -139,6 +143,28 @@ include passes/*/Makefile.inc
 include backends/*/Makefile.inc
 include techlibs/*/Makefile.inc
 
+else
+
+include frontends/verilog/Makefile.inc
+include frontends/ilang/Makefile.inc
+include frontends/ast/Makefile.inc
+
+OBJS += passes/hierarchy/hierarchy.o
+OBJS += passes/cmds/select.o
+OBJS += passes/cmds/show.o
+OBJS += passes/cmds/stat.o
+OBJS += passes/cmds/cover.o
+
+include passes/proc/Makefile.inc
+include passes/opt/Makefile.inc
+include passes/techmap/Makefile.inc
+include passes/abc/Makefile.inc
+
+include backends/verilog/Makefile.inc
+include backends/ilang/Makefile.inc
+
+endif
+
 top-all: $(TARGETS) $(EXTRA_TARGETS)
 
 yosys: $(OBJS)
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index c901da1c9..e54c018aa 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -2,10 +2,13 @@
 OBJS += passes/techmap/techmap.o
 OBJS += passes/techmap/simplemap.o
 OBJS += passes/techmap/dfflibmap.o
+OBJS += passes/techmap/libparse.o
+
+ifneq ($(SMALL),1)
 OBJS += passes/techmap/iopadmap.o
 OBJS += passes/techmap/hilomap.o
-OBJS += passes/techmap/libparse.o
 OBJS += passes/techmap/extract.o
+endif
 
 GENFILES += passes/techmap/stdcells.inc