From: Wesley W. Terpstra <wesley@sifive.com>
Date: Wed, 7 Dec 2016 21:21:20 +0000 (-0800)
Subject: LazyModule: provide Parameters
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45c491cd69b3dad347d88fdec3484d51814ee243;p=sifive-blocks.git

LazyModule: provide Parameters

This tracks PR #478 in rocketchip.
---

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 73ba3d0..4a0b3fc 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -11,9 +11,9 @@ import util.AsyncResetRegVec
 case class GPIOConfig(address: BigInt, width: Int)
 
 trait HasGPIOParameters {
-  val params: Tuple2[Parameters, GPIOConfig]
-  implicit val p = params._1
-  val c = params._2
+  implicit val p: Parameters
+  val params: GPIOConfig
+  val c = params
 }
 
 // YAGNI: Make the PUE, DS, and
@@ -289,7 +289,7 @@ object GPIOInputPinCtrl {
 }
 
 // Magic TL2 Incantation to create a TL2 Slave
-class TLGPIO(p: Parameters, c: GPIOConfig)
+class TLGPIO(c: GPIOConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle(Tuple2(p, c), _)    with GPIOBundle)(
-  new TLRegModule(Tuple2(p, c), _, _) with GPIOModule)
+  new TLRegBundle(c, _)    with GPIOBundle)(
+  new TLRegModule(c, _, _) with GPIOModule)
diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 414e713..f2fe586 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -8,7 +8,7 @@ import uncore.tilelink2.TLFragmenter
 
 trait PeripheryGPIO {
   this: TopNetwork { val gpioConfig: GPIOConfig } =>
-  val gpio = LazyModule(new TLGPIO(p, gpioConfig))
+  val gpio = LazyModule(new TLGPIO(gpioConfig))
   gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
   intBus.intnode := gpio.intnode
 }
diff --git a/src/main/scala/devices/mockaon/MockAON.scala b/src/main/scala/devices/mockaon/MockAON.scala
index 914a92c..15af109 100644
--- a/src/main/scala/devices/mockaon/MockAON.scala
+++ b/src/main/scala/devices/mockaon/MockAON.scala
@@ -21,9 +21,9 @@ case class MockAONConfig(
 }
 
 trait HasMockAONParameters {
-  val params: (MockAONConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
+  implicit val p: Parameters
+  val params: MockAONConfig
+  val c = params
 }
 
 class MockAONPMUIO extends Bundle {
@@ -99,7 +99,7 @@ trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
 
 }
 
-class MockAON(c: MockAONConfig)(implicit val p: Parameters)
+class MockAON(c: MockAONConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes, concurrency = 1)(
-  new TLRegBundle((c, p), _)    with MockAONBundle)(
-  new TLRegModule((c, p), _, _) with MockAONModule)
+  new TLRegBundle(c, _)    with MockAONBundle)(
+  new TLRegModule(c, _, _) with MockAONModule)
diff --git a/src/main/scala/devices/mockaon/MockAONWrapper.scala b/src/main/scala/devices/mockaon/MockAONWrapper.scala
index 15d755d..62afb89 100644
--- a/src/main/scala/devices/mockaon/MockAONWrapper.scala
+++ b/src/main/scala/devices/mockaon/MockAONWrapper.scala
@@ -27,7 +27,7 @@ class MockAONWrapperBundle extends Bundle {
   val rsts = new MockAONMOffRstIO()
 }
 
-class MockAONWrapper(c: MockAONConfig)(implicit val p: Parameters) extends LazyModule {
+class MockAONWrapper(c: MockAONConfig)(implicit p: Parameters) extends LazyModule {
 
   val node = TLAsyncInputNode()
   val intnode = IntOutputNode()
diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 2fd870c..c649e7e 100644
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -56,9 +56,9 @@ case class PWMBundleConfig(
 }
 
 trait HasPWMParameters {
-  val params: (PWMConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
+  implicit val p: Parameters
+  val params: PWMConfig
+  val c = params
 }
 
 trait PWMBundle extends Bundle with HasPWMParameters {
@@ -76,7 +76,7 @@ trait PWMModule extends Module with HasRegMap with HasPWMParameters {
   regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
 }
 
-class TLPWM(c: PWMConfig)(implicit val p: Parameters)
+class TLPWM(c: PWMConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle((c, p), _)    with PWMBundle)(
-  new TLRegModule((c, p), _, _) with PWMModule)
+  new TLRegBundle(c, _)    with PWMBundle)(
+  new TLRegModule(c, _, _) with PWMModule)
diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index bc920ea..f9954ce 100644
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -118,7 +118,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLS
       RegField.r(1, ip.rxwm)))
 }
 
-abstract class TLSPIBase(c: SPIConfigBase)(implicit val p: Parameters) extends LazyModule {
+abstract class TLSPIBase(c: SPIConfigBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
   val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
   val intnode = IntSourceNode(1)
diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 68b47fe..e696892 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -46,9 +46,9 @@ class UARTPortIO extends Bundle {
 }
 
 trait MixUARTParameters {
-  val params: (UARTConfig, Parameters)
-  val c = params._1
-  implicit val p = params._2
+  implicit val p: Parameters
+  val params: UARTConfig
+  val c = params
 }
 
 trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
@@ -269,7 +269,7 @@ class Majority(in: Set[Bool]) {
 }
 
 // Magic TL2 Incantation to create a TL2 Slave
-class UART(c: UARTConfig)(implicit val p: Parameters)
+class UART(c: UARTConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle((c, p), _)    with UARTTopBundle)(
-  new TLRegModule((c, p), _, _) with UARTTopModule)
+  new TLRegBundle(c, _)    with UARTTopBundle)(
+  new TLRegModule(c, _, _) with UARTTopModule)