From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 20 Mar 2022 13:18:21 +0000 (+0000)
Subject: fix Arty A7-100t PLL with quick demo
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45cc31443ef943d1043f91b6b326938bd0776a09;p=ls2.git

fix Arty A7-100t PLL with quick demo
---

diff --git a/src/arty_a7.py b/src/arty_a7.py
new file mode 100644
index 0000000..3361cec
--- /dev/null
+++ b/src/arty_a7.py
@@ -0,0 +1,15 @@
+from nmigen import Elaboratable, Module
+from nmigen_boards.test.blinky import Blinky
+from nmigen_boards.arty_a7 import ArtyA7_100Platform
+from arty_crg import ArtyA7CRG
+
+class BlinkyClocked(Elaboratable):
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.crg = ArtyA7CRG(25e6)
+        m.submodules.blinky = Blinky()
+        return m
+
+if __name__ == "__main__":
+    ArtyA7_100Platform(toolchain="yosys_nextpnr").build(BlinkyClocked(),
+                        do_program=True)
diff --git a/src/arty_crg.py b/src/arty_crg.py
index e1a7c65..ef57b0b 100644
--- a/src/arty_crg.py
+++ b/src/arty_crg.py
@@ -363,16 +363,9 @@ class ArtyA7CRG(Elaboratable):
         #m.domains += cd_eth
         m.domains += dramsync
 
-        clk100_ibuf = Signal()
-        clk100_buf  = Signal()
-        m.submodules += [
-            Instance("IBUF", i_I=clk100, o_O=clk100_ibuf),
-            Instance("BUFG", i_I=clk100_ibuf, o_O=clk100_buf)
-        ]
-
-        m.submodules.pll = pll = S7PLL(clk100_buf, speedgrade=-1)
+        m.submodules.pll = pll = S7PLL(clk100, speedgrade=-1)
         reset = platform.request(platform.default_rst).i
-        m.d.comb += pll.reset.eq(~reset)
+        m.d.comb += pll.reset.eq(reset)
         pll.set_clkin_freq(100e6)
 
         pll.create_clkout(sync, self.sys_clk_freq)