From: Florent Kermarrec Date: Mon, 13 Apr 2015 09:07:50 +0000 (+0200) Subject: liteeth: pep8 (E261, E271) X-Git-Tag: 24jan2021_ls180~2364 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45dc4920ec177197b9376c3446b296d994dae4c4;p=litex.git liteeth: pep8 (E261, E271) --- diff --git a/misoclib/com/liteeth/core/etherbone/record.py b/misoclib/com/liteeth/core/etherbone/record.py index 887169d8..4171c6f3 100644 --- a/misoclib/com/liteeth/core/etherbone/record.py +++ b/misoclib/com/liteeth/core/etherbone/record.py @@ -174,7 +174,7 @@ class LiteEthEtherboneRecord(Module): self.comb += [ Record.connect(sender.source, packetizer.sink), Record.connect(packetizer.source, source), - source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len), # XXX improve this + source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len), # XXX improve this source.ip_address.eq(last_ip_address) ] if endianness is "big": diff --git a/misoclib/com/liteeth/core/ip/checksum.py b/misoclib/com/liteeth/core/ip/checksum.py index 24d13ce9..7ad77b96 100644 --- a/misoclib/com/liteeth/core/ip/checksum.py +++ b/misoclib/com/liteeth/core/ip/checksum.py @@ -4,8 +4,8 @@ from misoclib.com.liteeth.generic import * class LiteEthIPV4Checksum(Module): def __init__(self, words_per_clock_cycle=1, skip_checksum=False): - self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog - self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog + self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog + self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog self.header = Signal(ipv4_header_len*8) self.value = Signal(16) self.done = Signal() diff --git a/misoclib/com/liteeth/core/udp/__init__.py b/misoclib/com/liteeth/core/udp/__init__.py index ec5ac2b7..f6a1dfdf 100644 --- a/misoclib/com/liteeth/core/udp/__init__.py +++ b/misoclib/com/liteeth/core/udp/__init__.py @@ -28,7 +28,7 @@ class LiteEthUDPTX(Module): packetizer.sink.src_port.eq(sink.src_port), packetizer.sink.dst_port.eq(sink.dst_port), packetizer.sink.length.eq(sink.length + udp_header_len), - packetizer.sink.checksum.eq(0), # Disabled (MAC CRC is enough) + packetizer.sink.checksum.eq(0), # Disabled (MAC CRC is enough) packetizer.sink.data.eq(sink.data) ] diff --git a/misoclib/com/liteeth/example_designs/test/test_udp.py b/misoclib/com/liteeth/example_designs/test/test_udp.py index 8d147292..6e98d07d 100644 --- a/misoclib/com/liteeth/example_designs/test/test_udp.py +++ b/misoclib/com/liteeth/example_designs/test/test_udp.py @@ -40,7 +40,7 @@ def check(p1, p2): def generate_packet(seed, length): r = [] for i in range(length): - r.append(seed_to_data(seed, True)%0xff) # XXX FIXME + r.append(seed_to_data(seed, True)%0xff) # XXX FIXME seed += 1 return r, seed @@ -66,7 +66,7 @@ def test(fpga_ip, udp_port, test_size): while tx_seed < test_size: tx_packet, tx_seed = generate_packet(tx_seed, 1024) tx_sock.sendto(bytes(tx_packet), (fpga_ip, udp_port)) - time.sleep(0.001) # XXX: FIXME, Python limitation? + time.sleep(0.001) # XXX: FIXME, Python limitation? receive_thread = threading.Thread(target=receive) receive_thread.start() diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py index f5f1168c..34ae2a82 100644 --- a/misoclib/com/liteeth/mac/frontend/sram.py +++ b/misoclib/com/liteeth/mac/frontend/sram.py @@ -11,7 +11,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): self.crc_error = Signal() slotbits = max(log2_int(nslots), 1) - lengthbits = log2_int(depth*4) # length in bytes + lengthbits = log2_int(depth*4) # length in bytes self._slot = CSRStatus(slotbits) self._length = CSRStatus(lengthbits) @@ -121,7 +121,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): self.source = source = Source(eth_phy_description(dw)) slotbits = max(log2_int(nslots), 1) - lengthbits = log2_int(depth*4) # length in bytes + lengthbits = log2_int(depth*4) # length in bytes self.lengthbits = lengthbits self._start = CSR() diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py index fdc349d2..10b17f79 100644 --- a/misoclib/com/liteeth/phy/gmii_mii.py +++ b/misoclib/com/liteeth/phy/gmii_mii.py @@ -86,7 +86,7 @@ class LiteEthGMIIMIIClockCounter(Module, AutoCSR): counter = RenameClockDomains(Counter(32), "eth_rx") self.submodules += counter self.comb += [ - counter.reset.eq(self._reset.storage), #slow, don't need CDC + counter.reset.eq(self._reset.storage), # slow, don't need CDC counter.ce.eq(1), ] self.specials += MultiReg(counter.value, self._value.status) diff --git a/misoclib/com/liteeth/test/model/arp.py b/misoclib/com/liteeth/test/model/arp.py index 22d61a1d..4cee649c 100644 --- a/misoclib/com/liteeth/test/model/arp.py +++ b/misoclib/com/liteeth/test/model/arp.py @@ -43,7 +43,7 @@ class ARPPacket(Packet): class ARP(Module): - def __init__(self, mac, mac_address, ip_address, debug=False): + def __init__(self, mac, mac_address, ip_address, debug=False): self.mac = mac self.mac_address = mac_address self.ip_address = ip_address diff --git a/misoclib/com/liteeth/test/model/etherbone.py b/misoclib/com/liteeth/test/model/etherbone.py index c88dee0b..fc43c2ef 100644 --- a/misoclib/com/liteeth/test/model/etherbone.py +++ b/misoclib/com/liteeth/test/model/etherbone.py @@ -285,7 +285,7 @@ class EtherbonePacket(Packet): class Etherbone(Module): - def __init__(self, udp, debug=False): + def __init__(self, udp, debug=False): self.udp = udp self.debug = debug self.tx_packets = [] @@ -301,7 +301,7 @@ class Etherbone(Module): print_etherbone(packet) udp_packet = udp.UDPPacket(packet) udp_packet.src_port = 0x1234 # XXX - udp_packet.dst_port = 20000 # XXX + udp_packet.dst_port = 20000 # XXX udp_packet.length = len(packet) udp_packet.checksum = 0 self.udp.send(udp_packet) diff --git a/misoclib/com/liteeth/test/model/icmp.py b/misoclib/com/liteeth/test/model/icmp.py index f5583628..bab9b334 100644 --- a/misoclib/com/liteeth/test/model/icmp.py +++ b/misoclib/com/liteeth/test/model/icmp.py @@ -41,7 +41,7 @@ class ICMPPacket(Packet): class ICMP(Module): - def __init__(self, ip, ip_address, debug=False): + def __init__(self, ip, ip_address, debug=False): self.ip = ip self.ip_address = ip_address self.debug = debug @@ -65,7 +65,7 @@ class ICMP(Module): ip_packet.fragment_offset = 0 ip_packet.ttl = 0x80 ip_packet.sender_ip = self.ip_address - ip_packet.target_ip = 0x12345678 # XXX + ip_packet.target_ip = 0x12345678 # XXX ip_packet.checksum = 0 ip_packet.protocol = icmp_protocol self.ip.send(ip_packet) diff --git a/misoclib/com/liteeth/test/model/ip.py b/misoclib/com/liteeth/test/model/ip.py index 825b4c08..4fe8be47 100644 --- a/misoclib/com/liteeth/test/model/ip.py +++ b/misoclib/com/liteeth/test/model/ip.py @@ -67,7 +67,7 @@ class IPPacket(Packet): class IP(Module): - def __init__(self, mac, mac_address, ip_address, debug=False, loopback=False): + def __init__(self, mac, mac_address, ip_address, debug=False, loopback=False): self.mac = mac self.mac_address = mac_address self.ip_address = ip_address @@ -95,7 +95,7 @@ class IP(Module): print_ip(">>>>>>>>") print_ip(packet) mac_packet = mac.MACPacket(packet) - mac_packet.target_mac = 0x12345678abcd # XXX + mac_packet.target_mac = 0x12345678abcd # XXX mac_packet.sender_mac = self.mac_address mac_packet.ethernet_type = ethernet_type_ip self.mac.send(mac_packet) diff --git a/misoclib/com/liteeth/test/model/mac.py b/misoclib/com/liteeth/test/model/mac.py index 80b39a86..41d41ab9 100644 --- a/misoclib/com/liteeth/test/model/mac.py +++ b/misoclib/com/liteeth/test/model/mac.py @@ -53,7 +53,7 @@ class MACPacket(Packet): self.preamble_error = self.check_remove_preamble() self.crc_error = self.check_remove_crc() if self.crc_error or self.preamble_error: - raise ValueError # XXX handle this properly + raise ValueError # XXX handle this properly else: self.decode_remove_header() @@ -89,7 +89,7 @@ class MACPacket(Packet): class MAC(Module): - def __init__(self, phy, debug=False, loopback=False): + def __init__(self, phy, debug=False, loopback=False): self.phy = phy self.debug = debug self.loopback = loopback @@ -129,7 +129,7 @@ class MAC(Module): if self.arp_callback is not None: self.arp_callback(packet) else: - raise ValueError # XXX handle this properly + raise ValueError # XXX handle this properly if __name__ == "__main__": from misoclib.com.liteeth.test.model.dumps import * diff --git a/misoclib/com/liteeth/test/model/udp.py b/misoclib/com/liteeth/test/model/udp.py index 7a82668f..fa61ccd6 100644 --- a/misoclib/com/liteeth/test/model/udp.py +++ b/misoclib/com/liteeth/test/model/udp.py @@ -41,7 +41,7 @@ class UDPPacket(Packet): class UDP(Module): - def __init__(self, ip, ip_address, debug=False, loopback=False): + def __init__(self, ip, ip_address, debug=False, loopback=False): self.ip = ip self.ip_address = ip_address self.debug = debug @@ -71,7 +71,7 @@ class UDP(Module): ip_packet.fragment_offset = 0 ip_packet.ttl = 0x80 ip_packet.sender_ip = self.ip_address - ip_packet.target_ip = 0x12345678 # XXX + ip_packet.target_ip = 0x12345678 # XXX ip_packet.checksum = 0 ip_packet.protocol = udp_protocol self.ip.send(ip_packet)