From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 26 Jan 2017 08:19:28 +0000 (+0100)
Subject: Be more conservative with merging large cells into FSMs
X-Git-Tag: yosys-0.8~531
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45e10c1c892a7f3082beb9a15aeaaada52267742;p=yosys.git

Be more conservative with merging large cells into FSMs
---

diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 0a2166b99..2c344a1c1 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -54,13 +54,27 @@ struct FsmExpand
 			if (cell->getPort("\\A").size() < 2)
 				return true;
 
+		int in_bits = 0;
 		RTLIL::SigSpec new_signals;
-		if (cell->hasPort("\\A"))
+
+		if (cell->hasPort("\\A")) {
+			in_bits += GetSize(cell->getPort("\\A"));
 			new_signals.append(assign_map(cell->getPort("\\A")));
-		if (cell->hasPort("\\B"))
+		}
+
+		if (cell->hasPort("\\B")) {
+			in_bits += GetSize(cell->getPort("\\B"));
 			new_signals.append(assign_map(cell->getPort("\\B")));
-		if (cell->hasPort("\\S"))
+		}
+
+		if (cell->hasPort("\\S")) {
+			in_bits += GetSize(cell->getPort("\\S"));
 			new_signals.append(assign_map(cell->getPort("\\S")));
+		}
+
+		if (in_bits > 8)
+			return false;
+
 		if (cell->hasPort("\\Y"))
 			new_signals.append(assign_map(cell->getPort("\\Y")));