From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 21 Mar 2015 17:41:59 +0000 (+0100)
Subject: sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
X-Git-Tag: 24jan2021_ls180~2460
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45eb5090dba31fabfce71e1051c8dc59817808f5;p=litex.git

sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
---

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 109e51d0..e41bced0 100644
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -49,6 +49,7 @@ class IS42S16160(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -7 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		20,
 		"tRCD":		20,
@@ -85,6 +86,7 @@ class AS4C16M16(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -6 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		18,
 		"tRCD":		18,