From: Michael Neuling <mikey@neuling.org>
Date: Thu, 2 Jul 2020 05:55:30 +0000 (+1000)
Subject: Add ram file to synthesis build dependencies
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45fd2354f2d238e2be4fa0a053fcb1f6a14d8e55;p=microwatt.git

Add ram file to synthesis build dependencies

Signed-off-by: Michael Neuling <mikey@neuling.org>
---

diff --git a/Makefile b/Makefile
index f20d048..769a6bd 100644
--- a/Makefile
+++ b/Makefile
@@ -175,10 +175,10 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
-microwatt.json: $(synth_files)
+microwatt.json: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" $(uart_files)
 
-microwatt.v: $(synth_files)
+microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files)
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall