From: enjoy-digital Date: Sat, 25 Apr 2020 06:27:00 +0000 (+0200) Subject: Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings X-Git-Tag: 24jan2021_ls180~440 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4608bd1864aae0c7a636334e0f6c1c51be51cb5d;p=litex.git Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings litex_sim: add option to create SDRAM module from SPD data --- 4608bd1864aae0c7a636334e0f6c1c51be51cb5d