From: Segher Boessenkool Date: Wed, 10 Dec 2014 18:33:26 +0000 (+0100) Subject: re PR target/64180 (PowerPC carry bit improvements) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46121d60c508a382e89bd7c4c403e981da09ee4a;p=gcc.git re PR target/64180 (PowerPC carry bit improvements) PR target/64180 * config/rs6000/rs6000.md (*add3_internal1): Rename to "*add3". (*add3_internal2, *add3_internal3, and (their splitters): Delete. (*add3_dot, *add3_dot2): New. (*add3_imm_dot, *add3_imm_dot2): New. From-SVN: r218593 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42afb65c719..8ed3e8c9f38 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2014-12-10 Segher Boessenkool + + PR target/64180 + * config/rs6000/rs6000.md (*add3_internal1): Rename to + "*add3". + (*add3_internal2, *add3_internal3, and (their splitters): + Delete. + (*add3_dot, *add3_dot2): New. + (*add3_imm_dot, *add3_imm_dot2): New. + 2014-12-10 Segher Boessenkool PR target/64180 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7a7475583a5..6712443e051 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1491,7 +1491,7 @@ } }) -(define_insn "*add3_internal1" +(define_insn "*add3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r") (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b") (match_operand:GPR 2 "add_operand" "r,I,L")))] @@ -1510,70 +1510,99 @@ "addis %0,%1,ha16(%2)" [(set_attr "type" "add")]) -(define_insn "*add3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) +(define_insn_and_split "*add3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:P 3 "=r,r,r,r"))] - "" + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode" "@ - add. %3,%1,%2 - addic. %3,%1,%2 - # + add. %0,%1,%2 #" - [(set_attr "type" "add,compare,compare,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (plus:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "add") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_short_operand" "")) +(define_insn_and_split "*add3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:GPR 3 ""))] - "reload_completed" - [(set (match_dup 3) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (plus:GPR (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) + (match_dup 2)))] + "mode == Pmode" + "@ + add. %0,%1,%2 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (plus:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "add") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) -(define_insn "*add3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) +(define_insn_and_split "*add3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "short_cint_operand" "I,I")) (const_int 0))) - (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") - (plus:P (match_dup 1) - (match_dup 2)))] - "" + (clobber (match_scratch:GPR 0 "=r,r")) + (clobber (reg:GPR CA_REGNO))] + "mode == Pmode" "@ - add. %0,%1,%2 addic. %0,%1,%2 - # #" - [(set_attr "type" "add,compare,compare,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (plus:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "add") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") - (match_operand:P 2 "reg_or_short_operand" "")) +(define_insn_and_split "*add3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "short_cint_operand" "I,I")) (const_int 0))) - (set (match_operand:P 0 "gpc_reg_operand" "") - (plus:P (match_dup 1) (match_dup 2)))] - "reload_completed" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (plus:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))] + "mode == Pmode" + "@ + addic. %0,%1,%2 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" [(set (match_dup 0) - (plus:P (match_dup 1) - (match_dup 2))) + (plus:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "add") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) ;; Split an add that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. Note that the low-order