From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 17 Oct 2023 13:37:46 +0000 (+0100)
Subject: added english language description for lwzupx instruction in  the pifixedload.mdwm
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4615705d0a819a5bad2f3c481df63d05755e8f93;p=openpower-isa.git

added english language description for lwzupx instruction in  the pifixedload.mdwm
---

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index f7528503..748b098e 100644
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -202,6 +202,16 @@ Pseudo-code:
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be the register RA.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None