From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 11:35:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2336
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4644d5a985a93f7031ed8d75b13055594aeb5ac3;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index f27479779..1c63c2c55 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -335,7 +335,7 @@ Remarkably, very little: the devil is in the details though.
   emergent characteristic from the carry-in, carry-out capability of
   Power ISA `adde` instruction. `sv.adde` as a BigNum add
   naturally emerges from the
-  sequential chaining of these scalar instructions.
+  sequential carry-flag chaining of these scalar instructions.
 * The Condition Register Fields of the Power ISA make a great candidate
   for use as Predicate Masks, particularly when combined with
   Vectorised `cmp` and Vectorised `crand`, `crxor` etc.