From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 12:19:26 +0000 (+0100)
Subject: tidyup, use FPModBaseChain and FPModBase
X-Git-Tag: ls180-24jan2020~632
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=465c201c3dfbf006b28aba6778eded0e8a1dc2e8;p=ieee754fpu.git

tidyup, use FPModBaseChain and FPModBase
---

diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py
index feed87f7..a3802b11 100644
--- a/src/ieee754/fpdiv/specialcases.py
+++ b/src/ieee754/fpdiv/specialcases.py
@@ -9,30 +9,26 @@ Relevant bugreports:
 * http://bugs.libre-riscv.org/show_bug.cgi?id=44
 """
 
-from nmigen import Module, Signal, Cat, Const, Elaboratable
+from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
+from ieee754.fpcommon.modbase import FPModBase, FPModBaseChain
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
-from nmutil.singlepipe import StageChain
-
-from ieee754.pipeline import DynamicPipe
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 from ieee754.fpmul.align import FPAlignModSingle
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DP
 
 
-class FPDIVSpecialCasesMod(Elaboratable):
+class FPDIVSpecialCasesMod(FPModBase):
     """ special cases: NaNs, infs, zeros, denormalised
         see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
     """
 
     def __init__(self, pspec):
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(pspec, "specialcases")
 
     def ispec(self):
         return FPADDBaseData(self.pspec)
@@ -40,15 +36,6 @@ class FPDIVSpecialCasesMod(Elaboratable):
     def ospec(self):
         return FPSCData(self.pspec, False)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.specialcases = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -64,13 +51,13 @@ class FPDIVSpecialCasesMod(Elaboratable):
                      self.o.b.eq(b1)
                      ]
 
+        # temporaries (used below)
         sabx = Signal(reset_less=True)   # sign a xor b (sabx, get it?)
-        comb += sabx.eq(a1.s ^ b1.s)
-
         abnan = Signal(reset_less=True)
-        comb += abnan.eq(a1.is_nan | b1.is_nan)
-
         abinf = Signal(reset_less=True)
+
+        comb += sabx.eq(a1.s ^ b1.s)
+        comb += abnan.eq(a1.is_nan | b1.is_nan)
         comb += abinf.eq(a1.is_inf & b1.is_inf)
 
         # select one of 3 different sets of specialcases (DIV, SQRT, RSQRT)
@@ -174,35 +161,15 @@ class FPDIVSpecialCasesMod(Elaboratable):
         return m
 
 
-class FPDIVSpecialCasesDeNorm(DynamicPipe):
+class FPDIVSpecialCasesDeNorm(FPModBaseChain):
     """ special cases: NaNs, infs, zeros, denormalised
     """
 
-    def __init__(self, pspec):
-        self.pspec = pspec
-        super().__init__(pspec)
-        self.out = self.ospec()
-
-    def ispec(self):
-        return FPADDBaseData(self.pspec)  # SpecialCases ispec
-
-    def ospec(self):
-        return FPSCData(self.pspec, False)  # Align ospec
-
-    def setup(self, m, i):
+    def get_chain(self):
         """ links module to inputs and outputs
         """
         smod = FPDIVSpecialCasesMod(self.pspec)
         dmod = FPAddDeNormMod(self.pspec, False)
         amod = FPAlignModSingle(self.pspec, False)
 
-        chain = StageChain([smod, dmod, amod])
-        chain.setup(m, i)
-
-        # only needed for break-out (early-out)
-        # self.out_do_z = smod.o.out_do_z
-
-        self.o = amod.o
-
-    def process(self, i):
-        return self.o
+        return [smod, dmod, amod]