From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 31 May 2020 12:19:35 +0000 (+0100)
Subject: still investigating
X-Git-Tag: div_pipeline~718
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46683c804f49a734e465e84a6d3c3a90f3284b9e;p=soc.git

still investigating
---

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 28c6b4d3..8b05976f 100644
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -92,6 +92,7 @@ class ALUMainStage(PipeModBase):
                 comb += src1.eq(a[0:8])
                 for i in range(8):
                     comb += eqs[i].eq(src1 == b[8*i:8*(i+1)])
+                comb += o.data[0].eq(eqs.any())
                 comb += cr0.data.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
                 comb += cr0.ok.eq(1)
 
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index a98d3440..56a8770a 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -147,7 +147,7 @@ class ALUTestCase(FHDLTestCase):
             self.run_tst_program(Program(lst), initial_regs)
 
     def test_cmpeqb(self):
-        lst = ["cmpeqb cr0, 1, 2"]
+        lst = ["cmpeqb cr1, 1, 2"]
         for i in range(20):
             initial_regs = [0] * 32
             initial_regs[1] = i