From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 19:14:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2422
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=466bf764cd75ba1fd4f5f5b56083d6d10768750e;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index bacaf933c..2fac410d7 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -254,7 +254,22 @@ of:
 
 * Defining the format of the prefix
 * Adding a `setvl` instruction
-* Adding SPRs and working out how to do context-switches
+* Adding Vector-context SPRs and working out how to do
+  context-switches with them
 * Writing an awful lot of Specification Documentation
   (4 years and counting)
 
+Once the basics of this concept have sunk in, advancements quickly
+follow:
+
+* Predication (an absolutely critical component for a Vector ISA).
+* Element-width overrides: most Scalar ISAs today are 64-bit only,
+  with primarily Load and Store being able to handle 8/16/32/64
+  and sometimes 128-bit (quad-word), where Vector ISAs need to
+  go as low as 8-bit arithmetic, even 8-bit Floating-Point for
+  high-performance AI.
+* "Reordering" of the assumption of linear sequential element
+  access, for Matrices, rotations, transposition, Convolutions,
+  DCT, FFT, Parallel Prefix-Sum and other common transformations
+  that require significant effort in other ISAs.
+