From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 22 Mar 2019 20:10:42 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7srl
X-Git-Tag: yosys-0.9~171^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46753cf89fd132d2ca8688053f4cf7247671d241;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7srl
---

46753cf89fd132d2ca8688053f4cf7247671d241
diff --cc techlibs/xilinx/cells_xtra.sh
index 46ababdea,56520ea10..3f8efeebd
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@@ -134,9 -135,9 +135,10 @@@ function xtract_cell_decl(
  	xtract_cell_decl ROM256X1
  	xtract_cell_decl ROM32X1
  	xtract_cell_decl ROM64X1
 -	xtract_cell_decl SRL16E
 -	xtract_cell_decl SRLC32E
 +	#xtract_cell_decl SRL16E
 +	#xtract_cell_decl SRLC32E
 +	xtract_cell_decl STARTUPE2
+ 	xtract_cell_decl STARTUPE2 "(* keep *)"
  	xtract_cell_decl USR_ACCESSE2
  	xtract_cell_decl XADC
  } > cells_xtra.new
diff --cc techlibs/xilinx/cells_xtra.v
index 6adad35ae,497518d35..06c868080
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@@ -3843,6 -3847,23 +3847,7 @@@ module ROM64X1 (...)
      input A0, A1, A2, A3, A4, A5;
  endmodule
  
 -module SRL16E (...);
 -    parameter [15:0] INIT = 16'h0000;
 -    parameter [0:0] IS_CLK_INVERTED = 1'b0;
 -    output Q;
 -    input A0, A1, A2, A3, CE, CLK, D;
 -endmodule
 -
 -module SRLC32E (...);
 -    parameter [31:0] INIT = 32'h00000000;
 -    parameter [0:0] IS_CLK_INVERTED = 1'b0;
 -    output Q;
 -    output Q31;
 -    input [4:0] A;
 -    input CE, CLK, D;
 -endmodule
 -
+ (* keep *)
  module STARTUPE2 (...);
      parameter PROG_USR = "FALSE";
      parameter real SIM_CCLK_FREQ = 0.0;