From: lkcl <lkcl@web>
Date: Sun, 24 May 2020 15:09:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2574
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4676033d9f307aaee1e25dad4f8915aca8c1987d;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 674b406a6..551d54a16 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -7,6 +7,10 @@ A minimum of 3 register files are required for POWER:
 * Control and Condition Code Registers (CR0-7, CTR, LR)
 * SPRs (Special Purpose Registers)
 
+Source code:
+
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
 # Regfile groups, Port Allocations and bit-widths