From: Anton Blanchard Date: Wed, 11 Dec 2019 01:24:46 +0000 (+1100) Subject: Dump CTR, LR and CR on sim termination, and update our tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=467630573c27251d68d7dbd80b6f6abcc3ba0f48;p=microwatt.git Dump CTR, LR and CR on sim termination, and update our tests Right now our test cases fold the SPRs into the GPRs. That makes debugging fails more difficult than it needs to be, so print out the CTR, LR and CR. We still need to print the XER, but that is in two spots in microwatt and will take some more work. This also adds many instructions to the tests that we have added lately including overflow instructions, CR logicals and mt/mfxer. Signed-off-by: Anton Blanchard --- diff --git a/core.vhdl b/core.vhdl index f95a1af..f4fe302 100644 --- a/core.vhdl +++ b/core.vhdl @@ -88,6 +88,8 @@ architecture behave of core is signal core_rst: std_ulogic; signal icache_rst: std_ulogic; + signal sim_cr_dump: std_ulogic; + -- Debug actions signal dbg_core_stop: std_ulogic; signal dbg_core_rst: std_ulogic; @@ -212,15 +214,20 @@ begin d_in => decode2_to_register_file, d_out => register_file_to_decode2, w_in => writeback_to_register_file, - sim_dump => terminate + sim_dump => terminate, + sim_dump_done => sim_cr_dump ); cr_file_0: entity work.cr_file + generic map ( + SIM => SIM + ) port map ( clk => clk, d_in => decode2_to_cr_file, d_out => cr_file_to_decode2, - w_in => writeback_to_cr_file + w_in => writeback_to_cr_file, + sim_dump => sim_cr_dump ); execute1_0: entity work.execute1 diff --git a/cr_file.vhdl b/cr_file.vhdl index dcd21be..a6dd585 100644 --- a/cr_file.vhdl +++ b/cr_file.vhdl @@ -6,13 +6,19 @@ library work; use work.common.all; entity cr_file is + generic ( + SIM : boolean := false + ); port( clk : in std_logic; d_in : in Decode2ToCrFileType; d_out : out CrFileToDecode2Type; - w_in : in WritebackToCrFileType + w_in : in WritebackToCrFileType; + + -- debug + sim_dump : in std_ulogic ); end entity cr_file; @@ -71,4 +77,15 @@ begin d_out.read_cr_data <= crs_updated; d_out.read_xerc_data <= xerc_updated; end process; + + sim_dump_test: if SIM generate + dump_cr: process(all) + begin + if sim_dump = '1' then + report "CR 00000000" & to_hstring(crs); + assert false report "end of test" severity failure; + end if; + end process; + end generate; + end architecture behaviour; diff --git a/register_file.vhdl b/register_file.vhdl index 952d9fc..2caa4b5 100644 --- a/register_file.vhdl +++ b/register_file.vhdl @@ -18,7 +18,8 @@ entity register_file is w_in : in WritebackToRegisterFileType; -- debug - sim_dump : in std_ulogic + sim_dump : in std_ulogic; + sim_dump_done : out std_ulogic ); end entity register_file; @@ -78,9 +79,15 @@ begin begin if sim_dump = '1' then loop_0: for i in 0 to 31 loop - report "REG " & to_hstring(registers(i)); + report "GPR" & integer'image(i) & " " & to_hstring(registers(i)); end loop loop_0; - assert false report "end of test" severity failure; + + report "LR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_LR))))); + report "CTR " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_CTR))))); + report "XER " & to_hstring(registers(to_integer(unsigned(fast_spr_num(SPR_XER))))); + sim_dump_done <= '1'; + else + sim_dump_done <= '0'; end if; end process; end generate; diff --git a/scripts/hash.py b/scripts/hash.py deleted file mode 100755 index 3b84a29..0000000 --- a/scripts/hash.py +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/python3 - -import re -import fileinput - -r = re.compile("REG ([0-9A-F]+)"); - -regs = list() - -for line in fileinput.input(): - m = r.search(line) - if m: - regs.append(int(m.group(1), 16)) - #print("%016X"% int(m.group(1), 16)) - -print("%x" % hash(tuple(regs))) diff --git a/scripts/run_test.sh b/scripts/run_test.sh index ef737fe..9fcb7ce 100755 --- a/scripts/run_test.sh +++ b/scripts/run_test.sh @@ -17,17 +17,18 @@ trap finish EXIT MICROWATT_DIR=$PWD -Y=$(${MICROWATT_DIR}/scripts/hash.py tests/${TEST}.out) - cd $TMPDIR cp ${MICROWATT_DIR}/tests/${TEST}.bin main_ram.bin -X=$( ${MICROWATT_DIR}/core_tb | ${MICROWATT_DIR}/scripts/hash.py ) +${MICROWATT_DIR}/core_tb | sed 's/.*: //' | egrep '^(GPR[0-9]|LR |CTR |XER |CR [0-9])' | sort | grep -v GPR31 | grep -v XER > test.out || true -if [ $X == $Y ]; then - echo "$TEST PASS" -else - echo "$TEST FAIL ********" - exit 1 -fi +grep -v "^$" ${MICROWATT_DIR}/tests/${TEST}.out | sort | grep -v GPR31 | grep -v XER > exp.out + +cp test.out /tmp +cp exp.out /tmp + +diff -q test.out exp.out && echo "$TEST PASS" && exit 0 + +echo "$TEST FAIL ********" +exit 1 diff --git a/tests/1.bin b/tests/1.bin index b7a11fc..dbff3a9 100644 Binary files a/tests/1.bin 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