From: Florent Kermarrec Date: Mon, 27 Apr 2020 21:08:15 +0000 (+0200) Subject: soc/cpu: rename cpu.buses to cpu.periph_buses. X-Git-Tag: 24jan2021_ls180~426 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=467fee3e236e21adb0debe6bd4be07bda4558b4d;p=litex.git soc/cpu: rename cpu.buses to cpu.periph_buses. --- diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 89766489..fe220cf2 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -73,12 +73,12 @@ class BlackParrotRV64(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.interrupt = Signal(4) - self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37) - self.buses = [idbus] + self.platform = platform + self.variant = variant + self.reset = Signal() + self.interrupt = Signal(4) + self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37) + self.periph_buses = [idbus] # # # diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 9ef8333b..e1b6bce3 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -34,13 +34,13 @@ class LM32(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.ibus = i = wishbone.Interface() - self.dbus = d = wishbone.Interface() - self.interrupt = Signal(32) - self.buses = [i, d] + self.platform = platform + self.variant = variant + self.reset = Signal() + self.ibus = i = wishbone.Interface() + self.dbus = d = wishbone.Interface() + self.interrupt = Signal(32) + self.periph_buses = [i, d] # # # diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 584ad445..17b6e3ea 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -41,12 +41,12 @@ class Microwatt(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=28) - self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=28) - self.buses = [wb_insn, wb_data] + self.platform = platform + self.variant = variant + self.reset = Signal() + self.wb_insn = wb_insn = wishbone.Interface(data_width=64, adr_width=28) + self.wb_data = wb_data = wishbone.Interface(data_width=64, adr_width=28) + self.periph_buses = [wb_insn, wb_data] # # # diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 2edbfe7e..1603fea7 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -31,13 +31,13 @@ class Minerva(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.ibus = wishbone.Interface() - self.dbus = wishbone.Interface() - self.buses = [self.ibus, self.dbus] - self.interrupt = Signal(32) + self.platform = platform + self.variant = variant + self.reset = Signal() + self.ibus = wishbone.Interface() + self.dbus = wishbone.Interface() + self.periph_buses = [self.ibus, self.dbus] + self.interrupt = Signal(32) # TODO: create variants self.with_icache = False diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index c82b6e55..59ece9ff 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -63,13 +63,13 @@ class MOR1KX(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.ibus = i = wishbone.Interface() - self.dbus = d = wishbone.Interface() - self.buses = [i, d] - self.interrupt = Signal(32) + self.platform = platform + self.variant = variant + self.reset = Signal() + self.ibus = i = wishbone.Interface() + self.dbus = d = wishbone.Interface() + self.periph_buses = [i, d] + self.interrupt = Signal(32) if variant == "linux": self.mem_map = self.mem_map_linux diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 304f6c14..03fc355d 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -56,13 +56,13 @@ class PicoRV32(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.idbus = idbus = wishbone.Interface() - self.buses = [idbus] - self.interrupt = Signal(32) - self.trap = Signal() + self.platform = platform + self.variant = variant + self.reset = Signal() + self.idbus = idbus = wishbone.Interface() + self.periph_buses = [idbus] + self.interrupt = Signal(32) + self.trap = Signal() # # # diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 14bab0f4..7d7afdf6 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -106,7 +106,7 @@ class RocketRV64(CPU): self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8)) - self.buses = [mmio_wb] + self.periph_buses = [mmio_wb] # # # diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index 4fb2f0a4..00f31349 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -31,12 +31,12 @@ class SERV(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant - self.reset = Signal() - self.ibus = ibus = wishbone.Interface() - self.dbus = dbus = wishbone.Interface() - self.buses = [ibus, dbus] + self.platform = platform + self.variant = variant + self.reset = Signal() + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() + self.periph_buses = [ibus, dbus] # # # diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 4e0bbc0a..bedd0de5 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -105,7 +105,7 @@ class VexRiscv(CPU, AutoCSR): self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() - self.buses = [ibus, dbus] + self.periph_buses = [ibus, dbus] self.interrupt = Signal(32) self.cpu_params = dict( diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index dcea829a..fbc86b6b 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -781,7 +781,7 @@ class SoC(Module): if reset_address is None: reset_address = self.mem_map["rom"] self.cpu.set_reset_address(reset_address) - for n, cpu_bus in enumerate(self.cpu.buses): + for n, cpu_bus in enumerate(self.cpu.periph_buses): self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus) self.csr.add("cpu", use_loc_if_exists=True) if hasattr(self.cpu, "interrupt"):