From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 29 Feb 2020 19:35:02 +0000 (-0500)
Subject: Minor cleanup
X-Git-Tag: div_pipeline~1813
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46a6002fd00ddcf57079460b5aa6730e4f734de2;p=soc.git

Minor cleanup
---

diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py
index c71fa155..5bab5537 100644
--- a/src/decoder/power_major_decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -3,11 +3,13 @@ import csv
 import os
 from enum import Enum, unique
 
+
 @unique
 class Function(Enum):
     ALU = 0
     LDST = 1
 
+
 @unique
 class InternalOp(Enum):
     OP_ADD = 0
@@ -23,20 +25,24 @@ class InternalOp(Enum):
     OP_TDI = 10
     OP_XOR = 11
 
+
 def get_csv(name):
     file_dir = os.path.dirname(os.path.realpath(__file__))
     with open(os.path.join(file_dir, name)) as csvfile:
         reader = csv.DictReader(csvfile)
         return list(reader)
 
+
 major_opcodes = get_csv("major.csv")
 
+
 class PowerMajorDecoder(Elaboratable):
     def __init__(self):
         self.opcode_in = Signal(6, reset_less=True)
 
         self.function_unit = Signal(Function, reset_less=True)
         self.internal_op = Signal(InternalOp, reset_less=True)
+
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -49,6 +55,7 @@ class PowerMajorDecoder(Elaboratable):
                     comb += self.internal_op.eq(InternalOp[row['internal op']])
         return m
 
-
-
-    
+    def ports(self):
+        return [self.opcode_in,
+                self.function_unit,
+                self.internal_op]
diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index 05d9b13c..321772eb 100644
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -1,12 +1,13 @@
-from nmigen import Module, Elaboratable, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 import sys
 import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
-                                InternalOp, major_opcodes)
+                                 InternalOp, major_opcodes)
+
 
 class DecoderTestCase(FHDLTestCase):
     def test_function_unit(self):
@@ -22,6 +23,7 @@ class DecoderTestCase(FHDLTestCase):
                  internal_op.eq(dut.internal_op)]
 
         sim = Simulator(m)
+
         def process():
             for row in major_opcodes:
                 yield opcode.eq(int(row['opcode']))
@@ -34,15 +36,16 @@ class DecoderTestCase(FHDLTestCase):
                 expected = InternalOp[row['internal op']].value
                 self.assertEqual(expected, result)
         sim.add_process(process)
-        with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]):
+        with sim.write_vcd("test.vcd", "test.gtkw", traces=[
+                opcode, function_unit, internal_op]):
             sim.run()
 
     def test_ilang(self):
         dut = PowerMajorDecoder()
-        vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit])
+        vl = rtlil.convert(dut, ports=dut.ports())
         with open("power_major_decoder.il", "w") as f:
             f.write(vl)
 
+
 if __name__ == "__main__":
     unittest.main()
-