From: Topi Pohjolainen Date: Tue, 17 Jan 2017 09:48:49 +0000 (+0200) Subject: i965/gen6: Issue direct depth stall and flush after depth clear X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46b346899d98e29943f8cd74c25bcb8d2f868a49;p=mesa.git i965/gen6: Issue direct depth stall and flush after depth clear instead of calling unconditionally brw_emit_mi_flush() which does: brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); Signed-off-by: Topi Pohjolainen Reviewed-by: Kenneth Graunke Reviewed-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 7fcde6c9692..ba9aa4b654b 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -234,7 +234,12 @@ brw_fast_clear_depth(struct gl_context *ctx) * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then * followed by Depth FLUSH' */ - brw_emit_mi_flush(brw); + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_DEPTH_STALL); + + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_CS_STALL); } /* Now, the HiZ buffer contains data that needs to be resolved to the depth