From: Samuel Pitoiset Date: Wed, 18 Sep 2019 08:58:04 +0000 (+0200) Subject: radv: fix writing depth/stencil clear values to image X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46b7512b0a73b24a00fa9308a44ab4ffe6054874;p=mesa.git radv: fix writing depth/stencil clear values to image Use the fastest way only if both aspects are used. Oops. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111728 Fixes: 218ce34962c ("radv: add mipmap support for the clear depth/stencil values") Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7e3dd7de534..f911af866be 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1585,8 +1585,8 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel); uint32_t level_count = radv_get_levelCount(image, range); - if (aspects & (VK_IMAGE_ASPECT_DEPTH_BIT | - VK_IMAGE_ASPECT_STENCIL_BIT)) { + if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | + VK_IMAGE_ASPECT_STENCIL_BIT)) { /* Use the fastest way when both aspects are used. */ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating)); radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | @@ -1605,10 +1605,11 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel + l); unsigned value; - if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) { + if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) { value = fui(ds_clear_value.depth); va += 4; } else { + assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT); value = ds_clear_value.stencil; }