From: Florent Kermarrec Date: Fri, 17 Jan 2020 11:27:21 +0000 (+0100) Subject: targets/kcu105: remove main_ram_size_limit X-Git-Tag: 24jan2021_ls180~731 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46c1c5c16f87954dc5947b49d5fb56d28cc670d4;p=litex.git targets/kcu105: remove main_ram_size_limit --- diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index be25e3c2..a6241173 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -96,8 +96,7 @@ class BaseSoC(SoCSDRAM): sdram_module = EDY4016A(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings, - main_ram_size_limit = 0x40000000) + timing_settings = sdram_module.timing_settings) # EthernetSoC --------------------------------------------------------------------------------------