From: Jacob Lifshay Date: Thu, 23 Mar 2023 01:15:00 +0000 (-0700) Subject: convert fcvttg[o] to fcvt[s]tg[o][.] X-Git-Tag: opf_rfc_ls001_v3~86 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46c263f1dd0ec5c5d513cae0d428341f2234abc7;p=libreriscv.git convert fcvttg[o] to fcvt[s]tg[o][.] --- diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 34f0cf3aa..9f27532a1 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -657,20 +657,19 @@ Section 7.1 of the ECMAScript / JavaScript ## Floating-point Convert To GPR -| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | -|-----|------|-------|-------|-------|-------|--------|----|--------|---------| -| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|----|----|---------| +| PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form | -`fcvttg RT, FRB, CVM, IT, RCS` -`fcvttgo RT, FRB, CVM, IT, RCS` +`fcvttg RT, FRB, CVM, IT` +`fcvttg. RT, FRB, CVM, IT` +`fcvttgo RT, FRB, CVM, IT` +`fcvttgo. RT, FRB, CVM, IT` ``` # based on xscvdpuxws reset_xflags() - if RCS[0] = 1 then # if Single mode - src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) - else - src <- bfp_CONVERT_FROM_BFP64((FRB)) + src <- bfp_CONVERT_FROM_BFP64((FRB)) switch(IT) case(0): # Signed 32-bit @@ -768,16 +767,15 @@ Section 7.1 of the ECMAScript / JavaScript FPSCR.FI <- 0 ``` -Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +Convert from 64-bit float in FRB to a unsigned/signed 32/64-bit integer in RT, with the conversion overflow/rounding semantics following the -chosen `CVM` value, following the usual 32-bit float in 64-bit float -format. `FPSCR` is modified and exceptions are raised as usual. +chosen `CVM` value. `FPSCR` is modified and exceptions are raised as usual. -Both of these instructions have an Rc=1 mode which sets CR0 in the normal +These instructions have an Rc=1 mode which sets CR0 in the normal way for any instructions producing a GPR result. Additionally, when OE=1, if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was -NaN) then this is considered to be an integer Overflow condition, and +NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions that overflow. @@ -789,35 +787,32 @@ Special Registers altered: ### Assembly Aliases -For brevity, `[o]` is used to mean `o` is optional there. +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|---------------------------|----------------------------|---------------------------|----------------------------| +| `fcvttgw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 0` | `fcvttgd RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 2` | +| `fcvttgw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 0` | `fcvttgd. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 2` | +| `fcvttgwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 0` | `fcvttgdo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 2` | +| `fcvttgwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 0` | `fcvttgdo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 2` | +| `fcvttguw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 1` | `fcvttgud RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 3` | +| `fcvttguw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 1` | `fcvttgud. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 3` | +| `fcvttguwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 1` | `fcvttgudo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 3` | +| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` | `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` | -| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | -|------------------------------|--------------------------------|------------------------------|--------------------------------| -| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | -| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | -| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | -| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | -| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | -| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | -| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | -| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | +## Floating-point Convert To GPR Single -## Floating-point Convert To GPR - -| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | -|-----|------|-------|-------|-------|-------|--------|----|--------|---------| -| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|----|----|---------| +| PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form | -`fcvttg RT, FRB, CVM, IT, RCS` -`fcvttgo RT, FRB, CVM, IT, RCS` +`fcvtstg RT, FRB, CVM, IT` +`fcvtstg. RT, FRB, CVM, IT` +`fcvtstgo RT, FRB, CVM, IT` +`fcvtstgo. RT, FRB, CVM, IT` ``` # based on xscvdpuxws reset_xflags() - if RCS[0] = 1 then # if Single mode - src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) - else - src <- bfp_CONVERT_FROM_BFP64((FRB)) + src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) switch(IT) case(0): # Signed 32-bit @@ -915,16 +910,16 @@ For brevity, `[o]` is used to mean `o` is optional there. FPSCR.FI <- 0 ``` -Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +Convert from 32-bit float in FRB to a unsigned/signed 32/64-bit integer in RT, with the conversion overflow/rounding semantics following the chosen `CVM` value, following the usual 32-bit float in 64-bit float format. `FPSCR` is modified and exceptions are raised as usual. -Both of these instructions have an Rc=1 mode which sets CR0 in the normal +These instructions have an Rc=1 mode which sets CR0 in the normal way for any instructions producing a GPR result. Additionally, when OE=1, if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was -NaN) then this is considered to be an integer Overflow condition, and +NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions that overflow. @@ -936,15 +931,13 @@ Special Registers altered: ### Assembly Aliases -For brevity, `[o]` is used to mean `o` is optional there. - -| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | -|------------------------------|--------------------------------|------------------------------|--------------------------------| -| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | -| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | -| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | -| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | -| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | -| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | -| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | -| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|----------------------------|-----------------------------|----------------------------|-----------------------------| +| `fcvtstgw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 0` | `fcvtstgd RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 2` | +| `fcvtstgw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 0` | `fcvtstgd. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 2` | +| `fcvtstgwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 0` | `fcvtstgdo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 2` | +| `fcvtstgwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 0` | `fcvtstgdo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 2` | +| `fcvtstguw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 1` | `fcvtstgud RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 3` | +| `fcvtstguw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 1` | `fcvtstgud. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 3` | +| `fcvtstguwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 1` | `fcvtstgudo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 3` | +| `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` | `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` | diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index 733b7e92d..24813e5a4 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -521,20 +521,19 @@ Section 7.1 of the ECMAScript / JavaScript ## Floating-point Convert To GPR -| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | -|-----|------|-------|-------|-------|-------|--------|----|--------|---------| -| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|----|----|---------| +| PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form | -`fcvttg RT, FRB, CVM, IT, RCS` -`fcvttgo RT, FRB, CVM, IT, RCS` +`fcvttg RT, FRB, CVM, IT` +`fcvttg. RT, FRB, CVM, IT` +`fcvttgo RT, FRB, CVM, IT` +`fcvttgo. RT, FRB, CVM, IT` ``` # based on xscvdpuxws reset_xflags() - if RCS[0] = 1 then # if Single mode - src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) - else - src <- bfp_CONVERT_FROM_BFP64((FRB)) + src <- bfp_CONVERT_FROM_BFP64((FRB)) switch(IT) case(0): # Signed 32-bit @@ -632,16 +631,15 @@ Section 7.1 of the ECMAScript / JavaScript FPSCR.FI <- 0 ``` -Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +Convert from 64-bit float in FRB to a unsigned/signed 32/64-bit integer in RT, with the conversion overflow/rounding semantics following the -chosen `CVM` value, following the usual 32-bit float in 64-bit float -format. `FPSCR` is modified and exceptions are raised as usual. +chosen `CVM` value. `FPSCR` is modified and exceptions are raised as usual. -Both of these instructions have an Rc=1 mode which sets CR0 in the normal +These instructions have an Rc=1 mode which sets CR0 in the normal way for any instructions producing a GPR result. Additionally, when OE=1, if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was -NaN) then this is considered to be an integer Overflow condition, and +NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions that overflow. @@ -653,39 +651,36 @@ Special Registers altered: ### Assembly Aliases -For brevity, `[o]` is used to mean `o` is optional there. - -| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | -|------------------------------|--------------------------------|------------------------------|--------------------------------| -| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | -| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | -| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | -| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | -| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | -| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | -| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | -| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|---------------------------|----------------------------|---------------------------|----------------------------| +| `fcvttgw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 0` | `fcvttgd RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 2` | +| `fcvttgw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 0` | `fcvttgd. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 2` | +| `fcvttgwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 0` | `fcvttgdo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 2` | +| `fcvttgwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 0` | `fcvttgdo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 2` | +| `fcvttguw RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 1` | `fcvttgud RT, FRB, CVM` | `fcvttg RT, FRB, CVM, 3` | +| `fcvttguw. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 1` | `fcvttgud. RT, FRB, CVM` | `fcvttg. RT, FRB, CVM, 3` | +| `fcvttguwo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 1` | `fcvttgudo RT, FRB, CVM` | `fcvttgo RT, FRB, CVM, 3` | +| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` | `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` | ---------- \newpage{} -## Floating-point Convert To GPR +## Floating-point Convert To GPR Single -| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-28 | 29 | 30 | 31 | Form | -|-----|------|-------|-------|-------|-------|--------|----|--------|---------| -| PO | RT | IT | CVM | FRB | XO | RCS[0] | OE | RCS[1] | XO-Form | +| 0-5 | 6-10 | 11-12 | 13-15 | 16-20 | 21-29 | 30 | 31 | Form | +|-----|------|-------|-------|-------|-------|----|----|---------| +| PO | RT | IT | CVM | FRB | XO | OE | Rc | XO-Form | -`fcvttg RT, FRB, CVM, IT, RCS` -`fcvttgo RT, FRB, CVM, IT, RCS` +`fcvtstg RT, FRB, CVM, IT` +`fcvtstg. RT, FRB, CVM, IT` +`fcvtstgo RT, FRB, CVM, IT` +`fcvtstgo. RT, FRB, CVM, IT` ``` # based on xscvdpuxws reset_xflags() - if RCS[0] = 1 then # if Single mode - src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) - else - src <- bfp_CONVERT_FROM_BFP64((FRB)) + src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) switch(IT) case(0): # Signed 32-bit @@ -783,16 +778,16 @@ For brevity, `[o]` is used to mean `o` is optional there. FPSCR.FI <- 0 ``` -Convert from 32/64-bit float in FRB to a unsigned/signed 32/64-bit integer +Convert from 32-bit float in FRB to a unsigned/signed 32/64-bit integer in RT, with the conversion overflow/rounding semantics following the chosen `CVM` value, following the usual 32-bit float in 64-bit float format. `FPSCR` is modified and exceptions are raised as usual. -Both of these instructions have an Rc=1 mode which sets CR0 in the normal +These instructions have an Rc=1 mode which sets CR0 in the normal way for any instructions producing a GPR result. Additionally, when OE=1, if the numerical value of the FP number is not 100% accurately preserved (due to truncation or saturation and including when the FP number was -NaN) then this is considered to be an integer Overflow condition, and +NaN) then this is considered to be an Integer Overflow condition, and CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions that overflow. @@ -804,18 +799,16 @@ Special Registers altered: ### Assembly Aliases -For brevity, `[o]` is used to mean `o` is optional there. - -| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | -|------------------------------|--------------------------------|------------------------------|--------------------------------| -| `fcvttgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 0` | -| `fcvttgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 1` | -| `fcvtstgw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 2` | -| `fcvtstgw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 2, 3` | -| `fcvttguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 0` | -| `fcvttguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 1` | -| `fcvtstguw[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 2` | -| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` | +| Assembly Alias | Full Instruction | Assembly Alias | Full Instruction | +|----------------------------|-----------------------------|----------------------------|-----------------------------| +| `fcvtstgw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 0` | `fcvtstgd RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 2` | +| `fcvtstgw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 0` | `fcvtstgd. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 2` | +| `fcvtstgwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 0` | `fcvtstgdo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 2` | +| `fcvtstgwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 0` | `fcvtstgdo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 2` | +| `fcvtstguw RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 1` | `fcvtstgud RT, FRB, CVM` | `fcvtstg RT, FRB, CVM, 3` | +| `fcvtstguw. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 1` | `fcvtstgud. RT, FRB, CVM` | `fcvtstg. RT, FRB, CVM, 3` | +| `fcvtstguwo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 1` | `fcvtstgudo RT, FRB, CVM` | `fcvtstgo RT, FRB, CVM, 3` | +| `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` | `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` | ----------