From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Feb 2021 13:18:16 +0000 (+0000)
Subject: add in SVSTATE.srcstep update, loop from 0 to VL-1
X-Git-Tag: convert-csv-opcode-to-binary~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46dac5251f464d04c52a11ff25d15d3aaefdeb3f;p=soc.git

add in SVSTATE.srcstep update, loop from 0 to VL-1
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 0a94fff9..14776199 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -977,6 +977,25 @@ class ISACaller:
                     self.gpr[regnum] = output
 
         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+
+        # check if it is the SVSTATE.src/dest step that needs incrementing
+        # this is our Sub-Program-Counter loop from 0 to VL-1
+        if self.is_svp64_mode:
+            # XXX twin predication TODO
+            vl = self.svstate.vl.asint(msb0=True)
+            mvl = self.svstate.maxvl.asint(msb0=True)
+            srcstep = self.svstate.srcstep.asint(msb0=True)
+            print ("    svstate.vl", vl)
+            print ("    svstate.mvl", mvl)
+            print ("    svstate.srcstep", srcstep)
+            # check if srcstep needs incrementing by one
+            if srcstep != vl-1:
+                self.svstate.srcstep += SelectableInt(1, 7)
+                return # DO NOT allow PC to update whilst Sub-PC loop running
+            # reset to zero
+            self.svstate.srcstep[0:7] = 0
+            print ("    svstate.srcstep loop end (PC to update)")
+
         # UPDATE program counter
         self.pc.update(self.namespace, self.is_svp64_mode)
 
diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 18044615..90f2d409 100644
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -17,14 +17,16 @@ from soc.sv.trans.svp64 import SVP64Asm
 class DecoderTestCase(FHDLTestCase):
 
     def test_sv_add(self):
-        isa = SVP64Asm(['sv.add 1, 2, 3'
+        isa = SVP64Asm(['sv.add 1, 5, 9'
                        ])
 
         lst = list(isa)
         print ("listing", lst)
         initial_regs = [0] * 32
-        initial_regs[3] = 0x1234
-        initial_regs[2] = 0x4321
+        initial_regs[9] = 0x1234
+        initial_regs[10] = 0x1111
+        initial_regs[5] = 0x4321
+        initial_regs[6] = 0x2223
         svstate = SVP64State()
         svstate.vl[0:7] = 2 # VL
         svstate.maxvl[0:7] = 2 # MAXVL