From: Claire Xenia Wolf <claire@symbioticeda.com>
Date: Thu, 1 Oct 2020 16:26:53 +0000 (+0200)
Subject: Ignore empty parameters in Verilog module instantiations
X-Git-Tag: working-ls180~251^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=46f0932c4c61aca3ab5332f99a4a60d110b52191;p=yosys.git

Ignore empty parameters in Verilog module instantiations

Fixes #2394

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8e5236639..678ce6c87 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1891,6 +1891,9 @@ cell_parameter:
 		astbuf1->children.push_back(node);
 		node->children.push_back($1);
 	} |
+	'.' TOK_ID '(' ')' {
+		// just ignore empty parameters
+	} |
 	'.' TOK_ID '(' expr ')' {
 		AstNode *node = new AstNode(AST_PARASET);
 		node->str = *$2;