From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Mar 2021 10:53:41 +0000 (+0100)
Subject: update Makefile to build 4ksrams
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47083f3531935d83fd1dfe98faf465cad8804cff;p=libresoc-litex.git

update Makefile to build 4ksrams
---

diff --git a/Makefile b/Makefile
index a56d541..bd7734e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,8 @@
 ls1804k:
 	./ls180soc.py --build --platform=ls180sram4k --num-srams=2
-	cp build/ls180/gateware/ls180.v .
-	cp build/ls180/gateware/mem.init .
-	cp build/ls180/gateware/mem_1.init .
-	cp build/ls180/gateware/mem_2.init .
-	cp build/ls180/gateware/mem_3.init .
-	cp build/ls180/gateware/mem_4.init .
+	cp build/ls180sram4k/gateware/ls180sram4k.v ./ls180.v
+	cp build/ls180sram4k/gateware/mem.init .
+	cp build/ls180sram4k/gateware/mem_1.init .
 	cp libresoc/libresoc.v .
 	yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'