From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 25 Jun 2020 12:17:41 +0000 (+0200)
Subject: Move combined assign tests to single file
X-Git-Tag: working-ls180~445^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=470df03f3d6731f0b784ceb4e1b05c8583b230a8;p=yosys.git

Move combined assign tests to single file

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
new file mode 100644
index 000000000..56fbac9de
--- /dev/null
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -0,0 +1,49 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a |= i;
+	a |= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a += i;
+        a += j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a ^= i;
+        a ^= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys
deleted file mode 100644
index 21e08550f..000000000
--- a/tests/opt/opt_expr_or_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a |= i;
-	a |= j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys
deleted file mode 100644
index 8d8ee5214..000000000
--- a/tests/opt/opt_expr_plus_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a += i;
-	a += j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys
deleted file mode 100644
index 924185e09..000000000
--- a/tests/opt/opt_expr_xor_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a ^= i;
-	a ^= j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i