From: lkcl <lkcl@web>
Date: Fri, 21 Apr 2023 00:07:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4717c71d6d9870c507f2387dbf4e30d5996964aa;p=libreriscv.git

---

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index b83989927..51d64c546 100644
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -59,7 +59,7 @@ as UnVectoriseable because there is only one `MSR`.
 UnVectorised instructions are required to be detected as such if Prefixed
 (either SVP64 or SVP64Single) and an Illegal Instruction Trap raised.
 
-*Architectural Note: Given that a "pre-classification" Decode Phase
+*Hardware Architectural Note: Given that a "pre-classification" Decode Phase
 is required (identifying whether the Suffix - Defined Word - is
 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding
 "UnVectorised" to this phase is not unreasonable.*