From: dh73 Date: Mon, 2 Oct 2017 00:59:45 +0000 (-0500) Subject: Tested and working altsyncarm without init files X-Git-Tag: yosys-0.8~307^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4718e65763854d9870bf9b88a7c1b1e78e10f05f;p=yosys.git Tested and working altsyncarm without init files --- diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v index b9938fe95..d8413159d 100755 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map.v @@ -31,44 +31,42 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A CFG_DBITS == 36 ? 9: 'bx; - localparam NUMWORDS = CFG_DBITS == 1 ? "8192": - CFG_DBITS == 2 ? "4096": - CFG_DBITS == 4 ? "2048": - CFG_DBITS == 8 ? "1024": - CFG_DBITS == 9 ? "1024": - CFG_DBITS == 16 ? "512": - CFG_DBITS == 18 ? "512": - CFG_DBITS == 32 ? "256": - CFG_DBITS == 36 ? "256": + localparam NUMWORDS = CFG_DBITS == 1 ? 8192: + CFG_DBITS == 2 ? 4096: + CFG_DBITS == 4 ? 2048: + CFG_DBITS == 8 ? 1024: + CFG_DBITS == 9 ? 1024: + CFG_DBITS == 16 ? 512: + CFG_DBITS == 18 ? 512: + CFG_DBITS == 32 ? 256: + CFG_DBITS == 36 ? 256: 'bx; - /* Killing some stupid warnings and assignations*/ - /* generate - if( MODE == 1 ) begin - assign B1DATA_t = ({34{1'b0},B1DATA[0]}); - end - endgenerate*/ - altsyncram #(.clock_enable_input_b ("ALTERNATE" ), - .clock_enable_input_a ("ALTERNATE" ), - .clock_enable_output_b ("NORMAL" ), - .clock_enable_output_a ("NORMAL" ), - .wrcontrol_aclr_a ("NONE" ), - .indata_aclr_a ("NONE" ), - .address_aclr_a ("NONE" ), - .outdata_aclr_a ("NONE" ), - .outdata_reg_a ("UNREGISTERED"), - .operation_mode ("SINGLE_PORT" ), - .intended_device_family ("CYCLONE IVE" ), - .outdata_reg_a ("UNREGISTERED"), - .lpm_type ("altsyncram" ), - .init_type ("unused" ), - .ram_block_type ("AUTO" ), - .numwords_b ( NUMWORDS ), - .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_ABITS ), - .width_b ( CFG_DBITS ), - .widthad_a ( CFG_ABITS ), - .width_a ( CFG_DBITS ) + altsyncram #(.clock_enable_input_b ("ALTERNATE" ), + .clock_enable_input_a ("ALTERNATE" ), + .clock_enable_output_b ("NORMAL" ), + .clock_enable_output_a ("NORMAL" ), + .wrcontrol_aclr_a ("NONE" ), + .indata_aclr_a ("NONE" ), + .address_aclr_a ("NONE" ), + .outdata_aclr_a ("NONE" ), + .outdata_reg_a ("UNREGISTERED"), + .operation_mode ("SINGLE_PORT" ), + .intended_device_family ("CYCLONE IVE" ), + .outdata_reg_a ("UNREGISTERED"), + .lpm_type ("altsyncram" ), + .init_type ("unused" ), + .ram_block_type ("AUTO" ), + .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value + .power_up_uninitialized ("FALSE"), + .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value + .width_byteena_a (1), // Forced value + .numwords_b ( NUMWORDS ), + .numwords_a ( NUMWORDS ), + .widthad_b ( CFG_ABITS ), + .width_b ( CFG_DBITS ), + .widthad_a ( CFG_ABITS ), + .width_a ( CFG_DBITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v index cf178db63..4370a105e 100755 --- a/techlibs/intel/common/m9k_bb.v +++ b/techlibs/intel/common/m9k_bb.v @@ -21,27 +21,31 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, addressstall_a, addressstall_b); - parameter clock_enable_input_b = "ALTERNATE"; - parameter clock_enable_input_a = "ALTERNATE"; - parameter clock_enable_output_b = "NORMAL"; - parameter clock_enable_output_a = "NORMAL"; - parameter wrcontrol_aclr_a = "NONE"; - parameter indata_aclr_a = "NONE"; - parameter address_aclr_a = "NONE"; - parameter outdata_aclr_a = "NONE"; - parameter outdata_reg_a = "UNREGISTERED"; - parameter operation_mode = "SINGLE_PORT"; - parameter intended_device_family = "MAX 10 FPGA"; - parameter outdata_reg_a = "UNREGISTERED"; - parameter lpm_type = "altsyncram"; - parameter init_type = "unused"; - parameter ram_block_type = "AUTO"; - parameter numwords_b = 0; - parameter numwords_a = 0; - parameter widthad_b = 1; - parameter width_b = 1; - parameter widthad_a = 1; - parameter width_a = 1; + parameter clock_enable_input_b = "ALTERNATE"; + parameter clock_enable_input_a = "ALTERNATE"; + parameter clock_enable_output_b = "NORMAL"; + parameter clock_enable_output_a = "NORMAL"; + parameter wrcontrol_aclr_a = "NONE"; + parameter indata_aclr_a = "NONE"; + parameter address_aclr_a = "NONE"; + parameter outdata_aclr_a = "NONE"; + parameter outdata_reg_a = "UNREGISTERED"; + parameter operation_mode = "SINGLE_PORT"; + parameter intended_device_family = "MAX 10 FPGA"; + parameter outdata_reg_a = "UNREGISTERED"; + parameter lpm_type = "altsyncram"; + parameter init_type = "unused"; + parameter ram_block_type = "AUTO"; + parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; + parameter power_up_uninitialized = "FALSE"; + parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ"; + parameter width_byteena_a = 1; + parameter numwords_b = 0; + parameter numwords_a = 0; + parameter widthad_b = 1; + parameter width_b = 1; + parameter widthad_a = 1; + parameter width_a = 1; // Port A declarations output [35:0] q_a;