From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Oct 2023 10:55:38 +0000 (+0100)
Subject: missing brackets in lhbrx
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=471acc0696f7cebfd2660cacfb7655c336aee27b;p=openpower-isa.git

missing brackets in lhbrx
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index ba0b5d1e..504ba839 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -357,7 +357,7 @@ Description:
     register RB shifted by (SH+1), and (RA|0).
 
     Bits 0:7 of the halfword in storage addressed by EA are
-    loaded into RT 56:63. Bits 8:15 of the halfword in storage
+    loaded into RT[56:63]. Bits 8:15 of the halfword in storage
     addressed by EA are loaded into RT[48:55].
     RT[0:47] are set to 0.