From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 13:04:09 +0000 (+0100)
Subject: optionally writing out CA/CA32 to XER
X-Git-Tag: div_pipeline~502
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47535d1379e851ac76fb5143eb7e865821467811;p=soc.git

optionally writing out CA/CA32 to XER
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index bb24035e..63b2cf0a 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -372,8 +372,11 @@ class ISACaller:
                 if isinstance(output, int):
                     output = SelectableInt(output, 256)
                 if name in ['CA', 'CA32']:
-                    print ("writing %s to XER" % name, output)
-                    self.spr['XER'][XER_bits[name]].eq(output)
+                    if carry_en:
+                        print ("writing %s to XER" % name, output)
+                        self.spr['XER'][XER_bits[name]].eq(output)
+                    else:
+                        print ("NOT writing %s to XER" % name, output)
                 elif name in info.special_regs:
                     print('writing special %s' % name, output, special_sprs)
                     if name in special_sprs: