From: Luke Kenneth Casson Leighton Date: Thu, 18 Jun 2020 17:05:59 +0000 (+0100) Subject: enable general test cases in test_issuer X-Git-Tag: div_pipeline~329^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=475faaa8f469d6c0de73ac9bd98b370664d6f1c8;p=soc.git enable general test cases in test_issuer --- diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index f5fc6dc8..0bd2b5ad 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -103,7 +103,7 @@ class TestRunner(FHDLTestCase): ins, code = instructions[index] print("instruction: 0x{:X}".format(ins & 0xffffffff)) - print(code) + print(index, code) # start the instruction yield go_insn_i.eq(1) @@ -119,6 +119,7 @@ class TestRunner(FHDLTestCase): # call simulated operation opname = code.split(' ')[0] yield from sim.call(opname) + yield Settle() index = sim.pc.CIA.value//4 # register check @@ -136,7 +137,7 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - #suite.addTest(TestRunner(GeneralTestCases.test_data)) + suite.addTest(TestRunner(GeneralTestCases.test_data)) suite.addTest(TestRunner(LDSTTestCase.test_data)) suite.addTest(TestRunner(CRTestCase.test_data)) suite.addTest(TestRunner(ShiftRotTestCase.test_data))