From: Christoph Bumiller <christoph.bumiller@speed.at>
Date: Fri, 16 May 2014 23:20:17 +0000 (+0200)
Subject: r600g: HW bug workaround for TGSI_OPCODE_BREAKC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=476aaf8b8ee77d84c295e1429035e92ecf3a7349;p=mesa.git

r600g: HW bug workaround for TGSI_OPCODE_BREAKC

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 67df2f2acd3..e75f7d622c6 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -143,6 +143,7 @@ void r600_bytecode_init(struct r600_bytecode *bc,
 
 	LIST_INITHEAD(&bc->cf);
 	bc->chip_class = chip_class;
+	bc->family = family;
 	bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
 	bc->stack.entry_size = stack_entry_size(family);
 }
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 4fb0ef06956..48ea3c4bc43 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -196,6 +196,7 @@ struct r600_stack_info {
 
 struct r600_bytecode {
 	enum chip_class			chip_class;
+	enum radeon_family		family;
 	bool				has_compressed_msaa_texturing;
 	int				type;
 	struct list_head		cf;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5823ba2e857..a4ed796b768 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -6280,10 +6280,26 @@ static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
 		return -EINVAL;
 	}
 
-	r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
-	if (r)
-		return r;
-	fc_set_mid(ctx, fscp);
+	if (ctx->bc->chip_class == EVERGREEN &&
+	    ctx->bc->family != CHIP_CYPRESS &&
+	    ctx->bc->family != CHIP_JUNIPER) {
+		/* HW bug: ALU_BREAK does not save the active mask correctly */
+		r = tgsi_uif(ctx);
+		if (r)
+			return r;
+
+		r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
+		if (r)
+			return r;
+		fc_set_mid(ctx, fscp);
+
+		return tgsi_endif(ctx);
+	} else {
+		r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
+		if (r)
+			return r;
+		fc_set_mid(ctx, fscp);
+	}
 
 	return 0;
 }