From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 9 Mar 2019 03:09:43 +0000 (-0800)
Subject: Correct incorrect output bit size
X-Git-Tag: div_pipeline~2337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=477aa040e1fcd08a76bbd378f59d140d4388113d;p=soc.git

Correct incorrect output bit size
---

diff --git a/TLB/src/AddressEncoder.py b/TLB/src/AddressEncoder.py
index c6437fc8..53e2479e 100644
--- a/TLB/src/AddressEncoder.py
+++ b/TLB/src/AddressEncoder.py
@@ -13,7 +13,7 @@ class AddressEncoder():
         # Output
         self.single_match = Signal(1)
         self.multiple_match = Signal(1)
-        self.o = Signal(width)
+        self.o = Signal(max=width)
         
     def elaborate(self, platform=None):
         m = Module()