From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 Jul 2022 15:11:53 +0000 (+0100)
Subject: add example fmvis instruction to trans/svp64.py
X-Git-Tag: sv_maxu_works-initial~220
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47835dbedc58dfab1ec1643981f76a478610fa72;p=openpower-isa.git

add example fmvis instruction to trans/svp64.py
---

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index a505496c..31d93e24 100644
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -27,7 +27,6 @@ oris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xori,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xoris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 subfic,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
-fmvis,NORMAL,,2P,EXTRA3,TODO,0,0,0,FRS,0,0,FRS,0,0,0
 cntlzw,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 cntlzd,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 subfze,NORMAL,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f669f0d1..86f00a8e 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1502,7 +1502,8 @@ if __name__ == '__main__':
     ]
     lst = [
         'sv.svstep./m=r3 2.v, 4, 0',
-        'ternlogi 0,0,0,0x5'
+        'ternlogi 0,0,0,0x5',
+        'fmvis 5,65535',
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list", list(isa))