From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Jul 2020 19:43:48 +0000 (+0100)
Subject: continue mul unit test debugging
X-Git-Tag: div_pipeline~162^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=478445c7684932e51db8640b502b699d2900bde2;p=soc.git

continue mul unit test debugging
---

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index 38e29a6a..ef1f100d 100644
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -77,7 +77,7 @@ class MulTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_mullw(self):
+    def test_0_mullw(self):
         lst = [f"mullw 3, 1, 2"]
         initial_regs = [0] * 32
         #initial_regs[1] = 0xffffffffffffffff
@@ -86,6 +86,28 @@ class MulTestCase(FHDLTestCase):
         initial_regs[2] = 0x2
         self.run_tst_program(Program(lst), initial_regs)
 
+    def tst_1_mullwo_(self):
+        lst = [f"mullwo. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x3b34b06f
+        initial_regs[2] = 0xfdeba998
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def tst_2_mullwo_(self):
+        lst = [f"mullwo. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffa988 # -5678
+        initial_regs[2] = 0xffffffffffffedcc # -1234
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_3_mullw(self):
+        for i in range(40):
+            lst = ["mullw 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst), initial_regs)
+
     def tst_rand_mullw(self):
         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
         for i in range(40):
diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index be95df68..7c24fa66 100644
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -24,17 +24,18 @@ class MulTestCases(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
-    def test_mullw(self):
-        lst = [f"addi 1, 0, 0x5678",
-               f"addi 2, 0, 0x1234",
-               f"mullw 3, 1, 2"]
+    def tst_mullw(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "mullw 3, 1, 2"]
         self.run_tst_program(Program(lst), [3])
 
-    def test_mullw(self):
-        lst = [f"addi 1, 0, 0x5678",
-                "neg 1, 1",
-               f"addi 2, 0, 0x1234",
-               f"mullw 3, 1, 2"]
+    def test_mullwo_(self):
+        lst = ["addi 1, 0, 0x5678",
+               "neg 1, 1",
+               "addi 2, 0, 0x1234",
+               "neg 2, 2",
+               "mullwo 3, 1, 2"]
         self.run_tst_program(Program(lst), [3])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index e6b09667..664deda1 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -289,13 +289,13 @@ class DecoderBase:
         print("sim pc", hex(sim.pc.CIA.value))
         print("sim cr", hex(sim_cr))
         print("sim xer", hex(sim_xer))
-        self.assertEqual(qcr, sim_cr)
         self.assertEqual(qpc, sim_pc)
         for reg in regs:
             qemu_val = qemu.get_register(reg)
             sim_val = sim.gpr(reg).value
             self.assertEqual(qemu_val, sim_val,
                              "expect %x got %x" % (qemu_val, sim_val))
+        self.assertEqual(qcr, sim_cr)
 
 
 class DecoderTestCase(DecoderBase, GeneralTestCases):