From: lkcl Date: Sun, 26 Mar 2023 11:36:24 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls001_v3~58 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4794155abcf2b79b98afff684ed856c020f2a60d;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn index 9ce790e97..b0c93da8b 100644 --- a/openpower/sv/rfc/ls008.mdwn +++ b/openpower/sv/rfc/ls008.mdwn @@ -81,6 +81,7 @@ TODO Add the following entries to: +* Section 1.3.2 Notation * the Appendices of Book I * Instructions of Book I as a new Section * SVL-Form of Book I Section 1.6.1.6 and 1.6.2 @@ -89,6 +90,20 @@ Add the following entries to: \newpage{} +# Notation, Section 1.3.2 + +When register operands (RA, RT, BF) are prefixed by a single underscore +(_RT, _RA, _BF) the variable contains the contents of the instruction field +not the contents of the Register File referenced *by* that field. Example: +`_RT` contains the contents of bits 5 thru 10. The relationship +`RT = GPR(_RT)` is thus always true. Uses include making alternative +decisions within an instruction based on whether the operand field +is zero or non-zero. + +---------------- + +\newpage{} + # svstep: Vertical-First Stepping and status reporting SVL-Form @@ -162,10 +177,10 @@ Pseudo-code: SVSTATE[7:13] <- VL if _RT != 0 then GPR(_RT) <- [0]*57 || VL - if ((¬vs) & ¬(ms)) = 0 then - # set requested Vertical-First mode, clear persist - SVSTATE[63] <- vf - SVSTATE[62] <- 0b0 + # MAXVL is a static "state-reset" opportunity so VF is only set then. + if ms = 1 then + SVSTATE[63] <- vf # set Vertical-First mode + SVSTATE[62] <- 0b0 # clear persist bit ``` Special Registers Altered: @@ -413,11 +428,12 @@ Add the following to Book I, 1.6.2 Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set Formats: SVL SVi (16:22) - Simple-V immediate field for setting VL or MVL (vl, maxvl in the SVSTATE SPR) + Simple-V immediate field used by setvl for setting VL or MVL + (vl, maxvl in the SVSTATE SPR) + and used as a "Mode of Operation" selector in svstep Formats: SVL ``` - # Appendices Appendix E Power ISA sorted by opcode @@ -428,4 +444,5 @@ Add the following to Book I, 1.6.2 | Form | Book | Page | Version | mnemonic | Description | |------|------|------|---------|----------|-------------| | SVL | I | # | 3.0B | svstep | Vertical-First Stepping and status reporting | +| SVL | I | # | 3.0B | setvl | Cray-like establishment of Looping (Vector) context |