From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 11 Jul 2017 15:38:19 +0000 (+0200)
Subject: Fix handling of x-bits in EDIF back-end
X-Git-Tag: yosys-0.8~391
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=479be3cec7a4ae5277720e75e215bc3d577261a9;p=yosys.git

Fix handling of x-bits in EDIF back-end
---

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 229b039b9..995aa2091 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -374,7 +374,17 @@ struct EdifBackend : public Backend {
 			}
 			for (auto &it : net_join_db) {
 				RTLIL::SigBit sig = it.first;
-				if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
+				if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
+					if (sig == RTLIL::State::Sx) {
+						for (auto &ref : it.second)
+							log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str());
+						sig = RTLIL::State::S0;
+					} else {
+						for (auto &ref : it.second)
+							log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str());
+						log_abort();
+					}
+				}
 					log_abort();
 				std::string netname;
 				if (sig == RTLIL::State::S0)