From: Cole Poirier <colepoirier@gmail.com>
Date: Wed, 12 Aug 2020 16:51:16 +0000 (-0700)
Subject: mmu.py fix or(block of logic) to be (block of logic).bool() https://bugs.libre-soc... 
X-Git-Tag: semi_working_ecp5~391
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47b48b7be241629557f68329abfd2aec47db77b7;p=soc.git

mmu.py fix or(block of logic) to be (block of logic).bool() https://bugs.libre-soc.org/show_bug.cgi?id=450#c31
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 16704f09..db677657 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -707,10 +707,9 @@ class MMU1(Elaboratable):
 #                           not finalmask(30 downto 0));
                 comb += mbits.eq(0 & r.mask_size)
                 comb += v.shift.eq(r.shift + (31 -12) - mbits)
-                # TODO need lkcl to check this is correct
-                comb += nonzero.eq(0 | Cat((~finalmask[0:31]),
-                                   r.addr[31:62]
-                                  ))
+                comb += nonzero.eq((
+                         r.addr[31:62] & ~finalmask[0:31]
+                        ).bool())
 #               if r.addr(63) /= r.addr(62) or nonzero = '1' then
 #                   v.state := RADIX_FINISH;
 #                   v.segerror := '1';