From: Jason Ekstrand Date: Thu, 18 Feb 2016 18:34:47 +0000 (-0800) Subject: Move isl to src/intel X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47b8b08612d44a43e43c3f6e95fe509ee3348723;p=mesa.git Move isl to src/intel --- diff --git a/configure.ac b/configure.ac index d6692b73ff1..604ea3728b4 100644 --- a/configure.ac +++ b/configure.ac @@ -2520,7 +2520,7 @@ AC_CONFIG_FILES([Makefile src/gtest/Makefile src/intel/Makefile src/intel/genxml/Makefile - src/isl/Makefile + src/intel/isl/Makefile src/loader/Makefile src/mapi/Makefile src/mapi/es1api/glesv1_cm.pc diff --git a/src/Makefile.am b/src/Makefile.am index 25b48c65009..02b83717755 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -58,7 +58,6 @@ AM_CXXFLAGS = $(VISIBILITY_CXXFLAGS) if HAVE_VULKAN SUBDIRS += intel -SUBDIRS += isl SUBDIRS += vulkan endif diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am index 0a6f411c7ba..520602dd290 100644 --- a/src/intel/Makefile.am +++ b/src/intel/Makefile.am @@ -19,4 +19,4 @@ # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS # IN THE SOFTWARE. -SUBDIRS = genxml +SUBDIRS = genxml isl diff --git a/src/intel/isl/.gitignore b/src/intel/isl/.gitignore new file mode 100644 index 00000000000..e9cfd67b94e --- /dev/null +++ b/src/intel/isl/.gitignore @@ -0,0 +1 @@ +/isl_format_layout.c diff --git a/src/intel/isl/Makefile.am b/src/intel/isl/Makefile.am new file mode 100644 index 00000000000..72f5460554f --- /dev/null +++ b/src/intel/isl/Makefile.am @@ -0,0 +1,90 @@ +# Copyright 2015 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +SUBDIRS = . + +noinst_LTLIBRARIES = libisl.la + +EXTRA_DIST = tests + +# The gallium includes are for the util/u_math.h include from main/macros.h +AM_CPPFLAGS = \ + $(INTEL_CFLAGS) \ + $(VALGRIND_CFLAGS) \ + $(DEFINES) \ + -I$(top_srcdir)/include \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/src/mapi \ + -I$(top_srcdir)/src/mesa \ + -I$(top_srcdir)/src/mesa/drivers/dri/common \ + -I$(top_srcdir)/src/mesa/drivers/dri/i965 \ + -I$(top_srcdir)/src/gallium/auxiliary \ + -I$(top_srcdir)/src/gallium/include \ + -I$(top_builddir)/src + +libisl_la_CFLAGS = $(CFLAGS) -Wno-override-init + +libisl_la_SOURCES = \ + isl.c \ + isl.h \ + isl_format.c \ + isl_format_layout.c \ + isl_gen4.c \ + isl_gen4.h \ + isl_gen6.c \ + isl_gen6.h \ + isl_gen7.c \ + isl_gen7.h \ + isl_gen8.c \ + isl_gen8.h \ + isl_gen9.c \ + isl_gen9.h \ + isl_image.c \ + $(NULL) + +BUILT_SOURCES = \ + isl_format_layout.c + +isl_format_layout.c: isl_format_layout_gen.bash \ + isl_format_layout.csv + $(AM_V_GEN)$(srcdir)/isl_format_layout_gen.bash \ + <$(srcdir)/isl_format_layout.csv >$@ + +# ---------------------------------------------------------------------------- +# Tests +# ---------------------------------------------------------------------------- + +TESTS = tests/isl_surf_get_image_offset_test + +check_PROGRAMS = $(TESTS) + +# Link tests to lib965_compiler.la for brw_get_device_info(). +tests_ldadd = \ + libisl.la \ + $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la + +tests_isl_surf_get_image_offset_test_SOURCES = \ + tests/isl_surf_get_image_offset_test.c +tests_isl_surf_get_image_offset_test_LDADD = $(tests_ldadd) + +# ---------------------------------------------------------------------------- + +include $(top_srcdir)/install-lib-links.mk diff --git a/src/intel/isl/README b/src/intel/isl/README new file mode 100644 index 00000000000..1ab4313fcc5 --- /dev/null +++ b/src/intel/isl/README @@ -0,0 +1,113 @@ +Intel Surface Layout + +Introduction +============ +isl is a small library that calculates the layout of Intel GPU surfaces, queries +those layouts, and queries the properties of surface formats. + + +Independence from User APIs +=========================== +isl's API is independent of any user-facing graphics API, such as OpenGL and +Vulkan. This independence allows isl to be used a shared component by multiple +Intel drivers. + +Rather than mimic the user-facing APIs, the isl API attempts to reflect Intel +hardware: the actual memory layout of Intel GPU surfaces and how one programs +the GPU to use those surfaces. For example: + + - The tokens of `enum isl_format` (such as `ISL_FORMAT_R8G8B8A8_UNORM`) + match those of the hardware enum `SURFACE_FORMAT` rather than the OpenGL + or Vulkan format tokens. And the values of `isl_format` and + `SURFACE_FORMAT` are identical. + + - The OpenGL and Vulkan APIs contain depth and stencil formats. However the + hardware enum `SURFACE_FORMAT` does not, and therefore neither does `enum + isl_format`. Rather than define new pixel formats that have no hardware + counterpart, isl records the intent to use a surface as a depth or stencil + buffer with the usage flags `ISL_SURF_USAGE_DEPTH_BIT` and + `ISL_SURF_USAGE_STENCIL_BIT`. + + - `struct isl_surf` distinguishes between the surface's logical dimension + from the user API's perspective (`enum isl_surf_dim`, which may be 1D, 2D, + or 3D) and the layout of those dimensions in memory (`enum isl_dim_layout`). + + +Surface Units +============= + +Intro +----- +ISL takes care in its equations to correctly handle conversion among surface +units (such as pixels and compression blocks) and to carefully distinguish +between a surface's logical layout in the client API and its physical layout +in memory. + +Symbol names often explicitly declare their unit with a suffix: + + - px: logical pixels + - sa: physical surface samples + - el: physical surface elements + - sa_rows: rows of physical surface samples + - el_rows: rows of physical surface elements + +Logical units are independent of hardware generation and are closely related +to the user-facing API (OpenGL and Vulkan). Physical units are dependent on +hardware generation and reflect the surface's layout in memory. + +Definitions +----------- +- Logical Pixels (px): + + The surface's layout from the perspective of the client API (OpenGL and + Vulkan) is in units of logical pixels. Logical pixels are independent of the + surface's layout in memory. + + A surface's width and height, in units of logical pixels, is not affected by + the surface's sample count. For example, consider a VkImage created with + VkImageCreateInfo{width=w0, height=h0, samples=s0}. The surface's width and + height at level 0 is, in units of logical pixels, w0 and h0 regardless of + the value of s0. + + For example, the logical array length of a 3D surface is always 1, even on + Gen9 where the surface's memory layout is that of an array surface + (ISL_DIM_LAYOUT_GEN4_2D). + +- Physical Surface Samples (sa): + + For a multisampled surface, this unit has the obvious meaning. + A singlesampled surface, from ISL's perspective, is simply a multisampled + surface whose sample count is 1. + + For example, consider a 2D single-level non-array surface with samples=4, + width_px=64, and height_px=64 (note that the suffix 'px' indicates logical + pixels). If the surface's multisample layout is ISL_MSAA_LAYOUT_INTERLEAVED, + then the extent of level 0 is, in units of physical surface samples, + width_sa=128, height_sa=128, depth_sa=1, array_length_sa=1. If + ISL_MSAA_LAYOUT_ARRAY, then width_sa=64, height_sa=64, depth_sa=1, + array_length_sa=4. + +- Physical Surface Elements (el): + + This unit allows ISL to treat compressed and uncompressed formats + identically in many calculations. + + If the surface's pixel format is compressed, such as ETC2, then a surface + element is equivalent to a compression block. If uncompressed, then + a surface element is equivalent to a surface sample. As a corollary, for + a given surface a surface element is at least as large as a surface sample. + +Errata +------ +ISL acquired the term 'surface element' from the Broadwell PRM [1], which +defines it as follows: + + An element is defined as a pixel in uncompresed surface formats, and as + a compression block in compressed surface formats. For MSFMT_DEPTH_STENCIL + type multisampled surfaces, an element is a sample. + + +References +========== +[1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >> + RENDER_SURFACE_STATE Surface Vertical Alignment (p325) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c new file mode 100644 index 00000000000..27928fd0850 --- /dev/null +++ b/src/intel/isl/isl.c @@ -0,0 +1,1428 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include + +#include "isl.h" +#include "isl_gen4.h" +#include "isl_gen6.h" +#include "isl_gen7.h" +#include "isl_gen8.h" +#include "isl_gen9.h" +#include "isl_priv.h" + +void PRINTFLIKE(3, 4) UNUSED +__isl_finishme(const char *file, int line, const char *fmt, ...) +{ + va_list ap; + char buf[512]; + + va_start(ap, fmt); + vsnprintf(buf, sizeof(buf), fmt, ap); + va_end(ap); + + fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); +} + +void +isl_device_init(struct isl_device *dev, + const struct brw_device_info *info, + bool has_bit6_swizzling) +{ + dev->info = info; + dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6; + dev->has_bit6_swizzling = has_bit6_swizzling; + + /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some + * device properties at buildtime. Verify that the macros with the device + * properties chosen during runtime. + */ + assert(ISL_DEV_GEN(dev) == dev->info->gen); + assert(ISL_DEV_USE_SEPARATE_STENCIL(dev) == dev->use_separate_stencil); + + /* Did we break hiz or stencil? */ + if (ISL_DEV_USE_SEPARATE_STENCIL(dev)) + assert(info->has_hiz_and_separate_stencil); + if (info->must_use_separate_stencil) + assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); +} + +/** + * @brief Query the set of multisamples supported by the device. + * + * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always + * supported. + */ +isl_sample_count_mask_t ATTRIBUTE_CONST +isl_device_get_sample_counts(struct isl_device *dev) +{ + if (ISL_DEV_GEN(dev) >= 9) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_2_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT | + ISL_SAMPLE_COUNT_16_BIT; + } else if (ISL_DEV_GEN(dev) >= 8) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_2_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT; + } else if (ISL_DEV_GEN(dev) >= 7) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT; + } else if (ISL_DEV_GEN(dev) >= 6) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_4_BIT; + } else { + return ISL_SAMPLE_COUNT_1_BIT; + } +} + +/** + * @param[out] info is written only on success + */ +bool +isl_tiling_get_info(const struct isl_device *dev, + enum isl_tiling tiling, + uint32_t format_block_size, + struct isl_tile_info *tile_info) +{ + const uint32_t bs = format_block_size; + uint32_t width, height; + + assert(bs > 0); + + switch (tiling) { + case ISL_TILING_LINEAR: + width = 1; + height = 1; + break; + + case ISL_TILING_X: + width = 1 << 9; + height = 1 << 3; + break; + + case ISL_TILING_Y0: + width = 1 << 7; + height = 1 << 5; + break; + + case ISL_TILING_W: + /* XXX: Should W tile be same as Y? */ + width = 1 << 6; + height = 1 << 6; + break; + + case ISL_TILING_Yf: + case ISL_TILING_Ys: { + if (ISL_DEV_GEN(dev) < 9) + return false; + + if (!isl_is_pow2(bs)) + return false; + + bool is_Ys = tiling == ISL_TILING_Ys; + + width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys)); + height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys)); + break; + } + } /* end switch */ + + *tile_info = (struct isl_tile_info) { + .tiling = tiling, + .width = width, + .height = height, + .size = width * height, + }; + + return true; +} + +void +isl_tiling_get_extent(const struct isl_device *dev, + enum isl_tiling tiling, + uint32_t format_block_size, + struct isl_extent2d *e) +{ + struct isl_tile_info tile_info; + isl_tiling_get_info(dev, tiling, format_block_size, &tile_info); + *e = isl_extent2d(tile_info.width, tile_info.height); +} + +/** + * @param[out] tiling is set only on success + */ +bool +isl_surf_choose_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling *tiling) +{ + isl_tiling_flags_t tiling_flags = info->tiling_flags; + + if (ISL_DEV_GEN(dev) >= 7) { + gen7_filter_tiling(dev, info, &tiling_flags); + } else { + isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev)); + gen7_filter_tiling(dev, info, &tiling_flags); + } + + #define CHOOSE(__tiling) \ + do { \ + if (tiling_flags & (1u << (__tiling))) { \ + *tiling = (__tiling); \ + return true; \ + } \ + } while (0) + + /* Of the tiling modes remaining, choose the one that offers the best + * performance. + */ + + if (info->dim == ISL_SURF_DIM_1D) { + /* Prefer linear for 1D surfaces because they do not benefit from + * tiling. To the contrary, tiling leads to wasted memory and poor + * memory locality due to the swizzling and alignment restrictions + * required in tiled surfaces. + */ + CHOOSE(ISL_TILING_LINEAR); + } + + CHOOSE(ISL_TILING_Ys); + CHOOSE(ISL_TILING_Yf); + CHOOSE(ISL_TILING_Y0); + CHOOSE(ISL_TILING_X); + CHOOSE(ISL_TILING_W); + CHOOSE(ISL_TILING_LINEAR); + + #undef CHOOSE + + /* No tiling mode accomodates the inputs. */ + return false; +} + +static bool +isl_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + if (ISL_DEV_GEN(dev) >= 8) { + return gen8_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else if (ISL_DEV_GEN(dev) >= 7) { + return gen7_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else if (ISL_DEV_GEN(dev) >= 6) { + return gen6_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else { + return gen4_choose_msaa_layout(dev, info, tiling, msaa_layout); + } +} + +static void +isl_msaa_interleaved_scale_px_to_sa(uint32_t samples, + uint32_t *width, uint32_t *height) +{ + assert(isl_is_pow2(samples)); + + /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level + * Sizes (p133): + * + * If the surface is multisampled and it is a depth or stencil surface + * or Multisampled Surface StorageFormat in SURFACE_STATE is + * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before + * proceeding: [...] + */ + if (width) + *width = isl_align(*width, 2) << ((ffs(samples) - 0) / 2); + if (height) + *height = isl_align(*height, 2) << ((ffs(samples) - 1) / 2); +} + +static enum isl_array_pitch_span +isl_choose_array_pitch_span(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + const struct isl_extent4d *phys_level0_sa) +{ + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + case ISL_DIM_LAYOUT_GEN4_2D: + if (ISL_DEV_GEN(dev) >= 8) { + /* QPitch becomes programmable in Broadwell. So choose the + * most compact QPitch possible in order to conserve memory. + * + * From the Broadwell PRM >> Volume 2d: Command Reference: Structures + * >> RENDER_SURFACE_STATE Surface QPitch (p325): + * + * - Software must ensure that this field is set to a value + * sufficiently large such that the array slices in the surface + * do not overlap. Refer to the Memory Data Formats section for + * information on how surfaces are stored in memory. + * + * - This field specifies the distance in rows between array + * slices. It is used only in the following cases: + * + * - Surface Array is enabled OR + * - Number of Mulitsamples is not NUMSAMPLES_1 and + * Multisampled Surface Storage Format set to MSFMT_MSS OR + * - Surface Type is SURFTYPE_CUBE + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } else if (ISL_DEV_GEN(dev) >= 7) { + /* Note that Ivybridge introduces + * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the + * driver more control over the QPitch. + */ + + if (phys_level0_sa->array_len == 1) { + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + if (isl_surf_usage_is_depth_or_stencil(info->usage)) { + /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >> + * Section 6.18.4.7: Surface Arrays (p112): + * + * If Surface Array Spacing is set to ARYSPC_FULL (note that + * the depth buffer and stencil buffer have an implied value of + * ARYSPC_FULL): + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + if (info->levels == 1) { + /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing + * to ARYSPC_LOD0. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + return ISL_ARRAY_PITCH_SPAN_FULL; + } else if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && + ISL_DEV_USE_SEPARATE_STENCIL(dev) && + isl_surf_usage_is_stencil(info->usage)) { + /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * The separate stencil buffer does not support mip mapping, thus + * the storage for LODs other than LOD 0 is not needed. + */ + assert(info->levels == 1); + assert(phys_level0_sa->array_len == 1); + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } else { + if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && + ISL_DEV_USE_SEPARATE_STENCIL(dev) && + isl_surf_usage_is_stencil(info->usage)) { + /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * The separate stencil buffer does not support mip mapping, + * thus the storage for LODs other than LOD 0 is not needed. + */ + assert(info->levels == 1); + assert(phys_level0_sa->array_len == 1); + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + if (phys_level0_sa->array_len == 1) { + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + return ISL_ARRAY_PITCH_SPAN_FULL; + } + + case ISL_DIM_LAYOUT_GEN4_3D: + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + unreachable("bad isl_dim_layout"); + return ISL_ARRAY_PITCH_SPAN_FULL; +} + +static void +isl_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + if (ISL_DEV_GEN(dev) >= 9) { + gen9_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); + } else if (ISL_DEV_GEN(dev) >= 8) { + gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); + } else if (ISL_DEV_GEN(dev) >= 7) { + gen7_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); + } else if (ISL_DEV_GEN(dev) >= 6) { + gen6_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); + } else { + gen4_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); + } +} + +static enum isl_dim_layout +isl_surf_choose_dim_layout(const struct isl_device *dev, + enum isl_surf_dim logical_dim) +{ + if (ISL_DEV_GEN(dev) >= 9) { + switch (logical_dim) { + case ISL_SURF_DIM_1D: + return ISL_DIM_LAYOUT_GEN9_1D; + case ISL_SURF_DIM_2D: + case ISL_SURF_DIM_3D: + return ISL_DIM_LAYOUT_GEN4_2D; + } + } else { + switch (logical_dim) { + case ISL_SURF_DIM_1D: + case ISL_SURF_DIM_2D: + return ISL_DIM_LAYOUT_GEN4_2D; + case ISL_SURF_DIM_3D: + return ISL_DIM_LAYOUT_GEN4_3D; + } + } + + unreachable("bad isl_surf_dim"); + return ISL_DIM_LAYOUT_GEN4_2D; +} + +/** + * Calculate the physical extent of the surface's first level, in units of + * surface samples. The result is aligned to the format's compression block. + */ +static void +isl_calc_phys_level0_extent_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent4d *phys_level0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + if (isl_format_is_yuv(info->format)) + isl_finishme("%s:%s: YUV format", __FILE__, __func__); + + switch (info->dim) { + case ISL_SURF_DIM_1D: + assert(info->height == 1); + assert(info->depth == 1); + assert(info->samples == 1); + assert(!isl_format_is_compressed(info->format)); + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN4_3D: + unreachable("bad isl_dim_layout"); + + case ISL_DIM_LAYOUT_GEN9_1D: + case ISL_DIM_LAYOUT_GEN4_2D: + *phys_level0_sa = (struct isl_extent4d) { + .w = info->width, + .h = 1, + .d = 1, + .a = info->array_len, + }; + break; + } + break; + + case ISL_SURF_DIM_2D: + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D); + + if (tiling == ISL_TILING_Ys && info->samples > 1) + isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__); + + switch (msaa_layout) { + case ISL_MSAA_LAYOUT_NONE: + assert(info->depth == 1); + assert(info->samples == 1); + + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align(info->width, fmtl->bw), + .h = isl_align(info->height, fmtl->bh), + .d = 1, + .a = info->array_len, + }; + break; + + case ISL_MSAA_LAYOUT_ARRAY: + assert(info->depth == 1); + assert(info->array_len == 1); + assert(!isl_format_is_compressed(info->format)); + + *phys_level0_sa = (struct isl_extent4d) { + .w = info->width, + .h = info->height, + .d = 1, + .a = info->samples, + }; + break; + + case ISL_MSAA_LAYOUT_INTERLEAVED: + assert(info->depth == 1); + assert(info->array_len == 1); + assert(!isl_format_is_compressed(info->format)); + + *phys_level0_sa = (struct isl_extent4d) { + .w = info->width, + .h = info->height, + .d = 1, + .a = 1, + }; + + isl_msaa_interleaved_scale_px_to_sa(info->samples, + &phys_level0_sa->w, + &phys_level0_sa->h); + break; + } + break; + + case ISL_SURF_DIM_3D: + assert(info->array_len == 1); + assert(info->samples == 1); + + if (fmtl->bd > 1) { + isl_finishme("%s:%s: compression block with depth > 1", + __FILE__, __func__); + } + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + unreachable("bad isl_dim_layout"); + + case ISL_DIM_LAYOUT_GEN4_2D: + assert(ISL_DEV_GEN(dev) >= 9); + + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align(info->width, fmtl->bw), + .h = isl_align(info->height, fmtl->bh), + .d = 1, + .a = info->depth, + }; + break; + + case ISL_DIM_LAYOUT_GEN4_3D: + assert(ISL_DEV_GEN(dev) < 9); + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align(info->width, fmtl->bw), + .h = isl_align(info->height, fmtl->bh), + .d = info->depth, + .a = 1, + }; + break; + } + break; + } +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN4_2D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen4_2d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(phys_level0_sa->depth == 1); + + if (info->levels == 1 && msaa_layout != ISL_MSAA_LAYOUT_INTERLEAVED) { + /* Do not pad the surface to the image alignment. Instead, pad it only + * to the pixel format's block alignment. + * + * For tiled surfaces, using a reduced alignment here avoids wasting CPU + * cycles on the below mipmap layout caluclations. Reducing the + * alignment here is safe because we later align the row pitch and array + * pitch to the tile boundary. It is safe even for + * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled + * to accomodate the interleaved samples. + * + * For linear surfaces, reducing the alignment here permits us to later + * choose an arbitrary, non-aligned row pitch. If the surface backs + * a VkBuffer, then an arbitrary pitch may be needed to accomodate + * VkBufferImageCopy::bufferRowLength. + */ + *phys_slice0_sa = (struct isl_extent2d) { + .w = isl_align_npot(phys_level0_sa->w, fmtl->bw), + .h = isl_align_npot(phys_level0_sa->h, fmtl->bh), + }; + return; + } + + uint32_t slice_top_w = 0; + uint32_t slice_bottom_w = 0; + uint32_t slice_left_h = 0; + uint32_t slice_right_h = 0; + + uint32_t W0 = phys_level0_sa->w; + uint32_t H0 = phys_level0_sa->h; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t H = isl_minify(H0, l); + + if (msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { + /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level + * Sizes (p133): + * + * If the surface is multisampled and it is a depth or stencil + * surface or Multisampled Surface StorageFormat in + * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be + * adjusted as follows before proceeding: [...] + */ + isl_msaa_interleaved_scale_px_to_sa(info->samples, &W, &H); + } + + uint32_t w = isl_align_npot(W, image_align_sa->w); + uint32_t h = isl_align_npot(H, image_align_sa->h); + + if (l == 0) { + slice_top_w = w; + slice_left_h = h; + slice_right_h = h; + } else if (l == 1) { + slice_bottom_w = w; + slice_left_h += h; + } else if (l == 2) { + slice_bottom_w += w; + slice_right_h += h; + } else { + slice_right_h += h; + } + } + + *phys_slice0_sa = (struct isl_extent2d) { + .w = MAX(slice_top_w, slice_bottom_w), + .h = MAX(slice_left_h, slice_right_h), + }; +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN4_3D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen4_3d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + assert(info->samples == 1); + assert(phys_level0_sa->array_len == 1); + + uint32_t slice_w = 0; + uint32_t slice_h = 0; + + uint32_t W0 = phys_level0_sa->w; + uint32_t H0 = phys_level0_sa->h; + uint32_t D0 = phys_level0_sa->d; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); + uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h); + uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d); + + uint32_t max_layers_horiz = MIN(level_d, 1u << l); + uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); + + slice_w = MAX(slice_w, level_w * max_layers_horiz); + slice_h += level_h * max_layers_vert; + } + + *phys_slice0_sa = (struct isl_extent2d) { + .w = slice_w, + .h = slice_h, + }; +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN9_1D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen9_1d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(phys_level0_sa->height == 1); + assert(phys_level0_sa->depth == 1); + assert(info->samples == 1); + assert(image_align_sa->w >= fmtl->bw); + + uint32_t slice_w = 0; + const uint32_t W0 = phys_level0_sa->w; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t w = isl_align_npot(W, image_align_sa->w); + + slice_w += w; + } + + *phys_slice0_sa = isl_extent2d(slice_w, 1); +} + +/** + * Calculate the physical extent of the surface's first array slice, in units + * of surface samples. If the surface is multi-leveled, then the result will + * be aligned to \a image_align_sa. + */ +static void +isl_calc_phys_slice0_extent_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info, + image_align_sa, phys_level0_sa, + phys_slice0_sa); + return; + case ISL_DIM_LAYOUT_GEN4_2D: + isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, + image_align_sa, phys_level0_sa, + phys_slice0_sa); + return; + case ISL_DIM_LAYOUT_GEN4_3D: + isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa, + phys_level0_sa, phys_slice0_sa); + return; + } +} + +/** + * Calculate the pitch between physical array slices, in units of rows of + * surface elements. + */ +static uint32_t +isl_calc_array_pitch_el_rows(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + enum isl_dim_layout dim_layout, + enum isl_array_pitch_span array_pitch_span, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + const struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + uint32_t pitch_sa_rows = 0; + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + /* Each row is an array slice */ + pitch_sa_rows = 1; + break; + case ISL_DIM_LAYOUT_GEN4_2D: + switch (array_pitch_span) { + case ISL_ARRAY_PITCH_SPAN_COMPACT: + pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); + break; + case ISL_ARRAY_PITCH_SPAN_FULL: { + /* The QPitch equation is found in the Broadwell PRM >> Volume 5: + * Memory Views >> Common Surface Formats >> Surface Layout >> 2D + * Surfaces >> Surface Arrays. + */ + uint32_t H0_sa = phys_level0_sa->h; + uint32_t H1_sa = isl_minify(H0_sa, 1); + + uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h); + uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h); + + uint32_t m; + if (ISL_DEV_GEN(dev) >= 7) { + /* The QPitch equation changed slightly in Ivybridge. */ + m = 12; + } else { + m = 11; + } + + pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h); + + if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 && + (info->height % 4 == 1)) { + /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than + * the value calculated in the equation above , for every + * other odd Surface Height starting from 1 i.e. 1,5,9,13. + * + * XXX(chadv): Is the errata natural corollary of the physical + * layout of interleaved samples? + */ + pitch_sa_rows += 4; + } + + pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh); + } /* end case */ + break; + } + break; + case ISL_DIM_LAYOUT_GEN4_3D: + assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); + pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); + break; + default: + unreachable("bad isl_dim_layout"); + break; + } + + assert(pitch_sa_rows % fmtl->bh == 0); + uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; + + if (ISL_DEV_GEN(dev) >= 9 && + info->dim == ISL_SURF_DIM_3D && + tile_info->tiling != ISL_TILING_LINEAR) { + /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch: + * + * Tile Mode != Linear: This field must be set to an integer multiple + * of the tile height + */ + pitch_el_rows = isl_align(pitch_el_rows, tile_info->height); + } + + return pitch_el_rows; +} + +/** + * Calculate the pitch of each surface row, in bytes. + */ +static uint32_t +isl_calc_row_pitch(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + uint32_t row_pitch = info->min_pitch; + + /* First, align the surface to a cache line boundary, as the PRM explains + * below. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Render Target and Media + * Surfaces: + * + * The data port accesses data (pixels) outside of the surface if they + * are contained in the same cache request as pixels that are within the + * surface. These pixels will not be returned by the requesting message, + * however if these pixels lie outside of defined pages in the GTT, + * a GTT error will result when the cache request is processed. In order + * to avoid these GTT errors, “padding” at the bottom of the surface is + * sometimes necessary. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: + * + * The sampling engine accesses texels outside of the surface if they + * are contained in the same cache line as texels that are within the + * surface. These texels will not participate in any calculation + * performed by the sampling engine and will not affect the result of + * any sampling engine operation, however if these texels lie outside of + * defined pages in the GTT, a GTT error will result when the cache line + * is accessed. In order to avoid these GTT errors, “padding” at the + * bottom and right side of a sampling engine surface is sometimes + * necessary. + * + * It is possible that a cache line will straddle a page boundary if the + * base address or pitch is not aligned. All pages included in the cache + * lines that are part of the surface must map to valid GTT entries to + * avoid errors. To determine the necessary padding on the bottom and + * right side of the surface, refer to the table in Alignment Unit Size + * section for the i and j parameters for the surface format in use. The + * surface must then be extended to the next multiple of the alignment + * unit size in each dimension, and all texels contained in this + * extended surface must have valid GTT entries. + * + * For example, suppose the surface size is 15 texels by 10 texels and + * the alignment parameters are i=4 and j=2. In this case, the extended + * surface would be 16 by 10. Note that these calculations are done in + * texels, and must be converted to bytes based on the surface format + * being used to determine whether additional pages need to be defined. + */ + assert(phys_slice0_sa->w % fmtl->bw == 0); + row_pitch = MAX(row_pitch, fmtl->bs * (phys_slice0_sa->w / fmtl->bw)); + + switch (tile_info->tiling) { + case ISL_TILING_LINEAR: + /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> + * RENDER_SURFACE_STATE Surface Pitch (p349): + * + * - For linear render target surfaces and surfaces accessed with the + * typed data port messages, the pitch must be a multiple of the + * element size for non-YUV surface formats. Pitch must be + * a multiple of 2 * element size for YUV surface formats. + * + * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we + * ignore because isl doesn't do buffers.] + * + * - For other linear surfaces, the pitch can be any multiple of + * bytes. + */ + if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { + if (isl_format_is_yuv(info->format)) { + row_pitch = isl_align_npot(row_pitch, 2 * fmtl->bs); + } else { + row_pitch = isl_align_npot(row_pitch, fmtl->bs); + } + } + break; + default: + /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> + * RENDER_SURFACE_STATE Surface Pitch (p349): + * + * - For tiled surfaces, the pitch must be a multiple of the tile + * width. + */ + row_pitch = isl_align(row_pitch, tile_info->width); + break; + } + + return row_pitch; +} + +/** + * Calculate the surface's total height, including padding, in units of + * surface elements. + */ +static uint32_t +isl_calc_total_height_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + uint32_t phys_array_len, + uint32_t row_pitch, + uint32_t array_pitch_el_rows) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + uint32_t total_h_el = phys_array_len * array_pitch_el_rows; + uint32_t pad_bytes = 0; + + /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Render Target and Media + * Surfaces: + * + * The data port accesses data (pixels) outside of the surface if they + * are contained in the same cache request as pixels that are within the + * surface. These pixels will not be returned by the requesting message, + * however if these pixels lie outside of defined pages in the GTT, + * a GTT error will result when the cache request is processed. In + * order to avoid these GTT errors, “padding” at the bottom of the + * surface is sometimes necessary. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: + * + * ... Lots of padding requirements, all listed separately below. + */ + + /* We can safely ignore the first padding requirement, quoted below, + * because isl doesn't do buffers. + * + * - [pre-BDW] For buffers, which have no inherent “height,” padding + * requirements are different. A buffer must be padded to the next + * multiple of 256 array elements, with an additional 16 bytes added + * beyond that to account for the L1 cache line. + */ + + /* + * - For compressed textures [...], padding at the bottom of the surface + * is to an even compressed row. + */ + if (isl_format_is_compressed(info->format)) + total_h_el = isl_align(total_h_el, 2); + + /* + * - For cube surfaces, an additional two rows of padding are required + * at the bottom of the surface. + */ + if (info->usage & ISL_SURF_USAGE_CUBE_BIT) + total_h_el += 2; + + /* + * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats, + * additional padding is required. These surfaces require an extra row + * plus 16 bytes of padding at the bottom in addition to the general + * padding requirements. + */ + if (isl_format_is_yuv(info->format) && + (fmtl->bs == 96 || fmtl->bs == 48|| fmtl->bs == 24)) { + total_h_el += 1; + pad_bytes += 16; + } + + /* + * - For linear surfaces, additional padding of 64 bytes is required at + * the bottom of the surface. This is in addition to the padding + * required above. + */ + if (tile_info->tiling == ISL_TILING_LINEAR) + pad_bytes += 64; + + /* The below text weakens, not strengthens, the padding requirements for + * linear surfaces. Therefore we can safely ignore it. + * + * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array, + * non-MSAA, non-mip-mapped surfaces in linear memory, the only + * padding requirement is to the next aligned 64-byte boundary beyond + * the end of the surface. The rest of the padding requirements + * documented above do not apply to these surfaces. + */ + + /* + * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and + * height % 4 != 0, the surface must be padded with + * 4-(height % 4)*Surface Pitch # of bytes. + */ + if (ISL_DEV_GEN(dev) >= 9 && + tile_info->tiling == ISL_TILING_LINEAR && + (info->dim == ISL_SURF_DIM_2D || info->dim == ISL_SURF_DIM_3D)) { + total_h_el = isl_align(total_h_el, 4); + } + + /* + * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded + * to 4 times the Surface Pitch # of bytes + */ + if (ISL_DEV_GEN(dev) >= 9 && + tile_info->tiling == ISL_TILING_LINEAR && + info->dim == ISL_SURF_DIM_1D) { + total_h_el += 4; + } + + /* Be sloppy. Align any leftover padding to a row boundary. */ + total_h_el += isl_align_div_npot(pad_bytes, row_pitch); + + return total_h_el; +} + +bool +isl_surf_init_s(const struct isl_device *dev, + struct isl_surf *surf, + const struct isl_surf_init_info *restrict info) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + const struct isl_extent4d logical_level0_px = { + .w = info->width, + .h = info->height, + .d = info->depth, + .a = info->array_len, + }; + + enum isl_dim_layout dim_layout = + isl_surf_choose_dim_layout(dev, info->dim); + + enum isl_tiling tiling; + if (!isl_surf_choose_tiling(dev, info, &tiling)) + return false; + + struct isl_tile_info tile_info; + if (!isl_tiling_get_info(dev, tiling, fmtl->bs, &tile_info)) + return false; + + enum isl_msaa_layout msaa_layout; + if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout)) + return false; + + struct isl_extent3d image_align_el; + isl_choose_image_alignment_el(dev, info, tiling, msaa_layout, + &image_align_el); + + struct isl_extent3d image_align_sa = + isl_extent3d_el_to_sa(info->format, image_align_el); + + struct isl_extent4d phys_level0_sa; + isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout, + &phys_level0_sa); + assert(phys_level0_sa.w % fmtl->bw == 0); + assert(phys_level0_sa.h % fmtl->bh == 0); + + enum isl_array_pitch_span array_pitch_span = + isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa); + + struct isl_extent2d phys_slice0_sa; + isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout, + &image_align_sa, &phys_level0_sa, + &phys_slice0_sa); + assert(phys_slice0_sa.w % fmtl->bw == 0); + assert(phys_slice0_sa.h % fmtl->bh == 0); + + const uint32_t row_pitch = isl_calc_row_pitch(dev, info, &tile_info, + &image_align_sa, + &phys_slice0_sa); + + const uint32_t array_pitch_el_rows = + isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout, + array_pitch_span, &image_align_sa, + &phys_level0_sa, &phys_slice0_sa); + + const uint32_t total_h_el = + isl_calc_total_height_el(dev, info, &tile_info, + phys_level0_sa.array_len, row_pitch, + array_pitch_el_rows); + + const uint32_t total_h_sa = total_h_el * fmtl->bh; + const uint32_t size = row_pitch * isl_align(total_h_sa, tile_info.height); + + /* Alignment of surface base address, in bytes */ + uint32_t base_alignment = MAX(1, info->min_alignment); + assert(isl_is_pow2(base_alignment) && isl_is_pow2(tile_info.size)); + base_alignment = MAX(base_alignment, tile_info.size); + + *surf = (struct isl_surf) { + .dim = info->dim, + .dim_layout = dim_layout, + .msaa_layout = msaa_layout, + .tiling = tiling, + .format = info->format, + + .levels = info->levels, + .samples = info->samples, + + .image_alignment_el = image_align_el, + .logical_level0_px = logical_level0_px, + .phys_level0_sa = phys_level0_sa, + + .size = size, + .alignment = base_alignment, + .row_pitch = row_pitch, + .array_pitch_el_rows = array_pitch_el_rows, + .array_pitch_span = array_pitch_span, + + .usage = info->usage, + }; + + return true; +} + +void +isl_surf_get_tile_info(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_tile_info *tile_info) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + isl_tiling_get_info(dev, surf->tiling, fmtl->bs, tile_info); +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN4_2D. + */ +static void +get_image_offset_sa_gen4_2d(const struct isl_surf *surf, + uint32_t level, uint32_t layer, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(layer < surf->phys_level0_sa.array_len); + assert(surf->phys_level0_sa.depth == 1); + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + const uint32_t W0 = surf->phys_level0_sa.width; + const uint32_t H0 = surf->phys_level0_sa.height; + + uint32_t x = 0; + uint32_t y = layer * isl_surf_get_array_pitch_sa_rows(surf); + + for (uint32_t l = 0; l < level; ++l) { + if (l == 1) { + uint32_t W = isl_minify(W0, l); + + if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) + isl_msaa_interleaved_scale_px_to_sa(surf->samples, &W, NULL); + + x += isl_align_npot(W, image_align_sa.w); + } else { + uint32_t H = isl_minify(H0, l); + + if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) + isl_msaa_interleaved_scale_px_to_sa(surf->samples, NULL, &H); + + y += isl_align_npot(H, image_align_sa.h); + } + } + + *x_offset_sa = x; + *y_offset_sa = y; +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN4_3D. + */ +static void +get_image_offset_sa_gen4_3d(const struct isl_surf *surf, + uint32_t level, uint32_t logical_z_offset_px, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level)); + assert(surf->phys_level0_sa.array_len == 1); + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + const uint32_t W0 = surf->phys_level0_sa.width; + const uint32_t H0 = surf->phys_level0_sa.height; + const uint32_t D0 = surf->phys_level0_sa.depth; + + uint32_t x = 0; + uint32_t y = 0; + + for (uint32_t l = 0; l < level; ++l) { + const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h); + const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d); + const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); + + y += level_h * max_layers_vert; + } + + const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w); + const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h); + const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d); + + const uint32_t max_layers_horiz = MIN(level_d, 1u << level); + + x += level_w * (logical_z_offset_px % max_layers_horiz); + y += level_h * (logical_z_offset_px / max_layers_horiz); + + *x_offset_sa = x; + *y_offset_sa = y; +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN9_1D. + */ +static void +get_image_offset_sa_gen9_1d(const struct isl_surf *surf, + uint32_t level, uint32_t layer, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(layer < surf->phys_level0_sa.array_len); + assert(surf->phys_level0_sa.height == 1); + assert(surf->phys_level0_sa.depth == 1); + assert(surf->samples == 1); + + const uint32_t W0 = surf->phys_level0_sa.width; + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + uint32_t x = 0; + + for (uint32_t l = 0; l < level; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t w = isl_align_npot(W, image_align_sa.w); + + x += w; + } + + *x_offset_sa = x; + *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf); +} + +/** + * Calculate the offset, in units of surface samples, to a subimage in the + * surface. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +static void +get_image_offset_sa(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(logical_array_layer < surf->logical_level0_px.array_len); + assert(logical_z_offset_px + < isl_minify(surf->logical_level0_px.depth, level)); + + switch (surf->dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + get_image_offset_sa_gen9_1d(surf, level, logical_array_layer, + x_offset_sa, y_offset_sa); + break; + case ISL_DIM_LAYOUT_GEN4_2D: + get_image_offset_sa_gen4_2d(surf, level, logical_array_layer + + logical_z_offset_px, + x_offset_sa, y_offset_sa); + break; + case ISL_DIM_LAYOUT_GEN4_3D: + get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px, + x_offset_sa, y_offset_sa); + break; + } +} + +void +isl_surf_get_image_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_el, + uint32_t *y_offset_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + assert(level < surf->levels); + assert(logical_array_layer < surf->logical_level0_px.array_len); + assert(logical_z_offset_px + < isl_minify(surf->logical_level0_px.depth, level)); + + uint32_t x_offset_sa, y_offset_sa; + get_image_offset_sa(surf, level, + logical_array_layer, + logical_z_offset_px, + &x_offset_sa, + &y_offset_sa); + + *x_offset_el = x_offset_sa / fmtl->bw; + *y_offset_el = y_offset_sa / fmtl->bh; +} + +void +isl_surf_get_image_intratile_offset_el(const struct isl_device *dev, + const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset, + uint32_t *base_address_offset, + uint32_t *x_offset_el, + uint32_t *y_offset_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + struct isl_tile_info tile_info; + isl_surf_get_tile_info(dev, surf, &tile_info); + + uint32_t total_x_offset_el; + uint32_t total_y_offset_el; + isl_surf_get_image_offset_el(surf, level, + logical_array_layer, + logical_z_offset, + &total_x_offset_el, + &total_y_offset_el); + + uint32_t small_y_offset_el = total_y_offset_el % tile_info.height; + uint32_t big_y_offset_el = total_y_offset_el - small_y_offset_el; + uint32_t big_y_offset_B = big_y_offset_el * surf->row_pitch; + + uint32_t total_x_offset_B = total_x_offset_el * fmtl->bs; + uint32_t small_x_offset_B = total_x_offset_B % tile_info.width; + uint32_t small_x_offset_el = small_x_offset_B / fmtl->bs; + uint32_t big_x_offset_B = total_x_offset_B - small_x_offset_B; + + *base_address_offset = big_y_offset_B + big_x_offset_B; + *x_offset_el = small_x_offset_el; + *y_offset_el = small_y_offset_el; +} + +uint32_t +isl_surf_get_depth_format(const struct isl_device *dev, + const struct isl_surf *surf) +{ + /* Support for separate stencil buffers began in gen5. Support for + * interleaved depthstencil buffers ceased in gen7. The intermediate gens, + * those that supported separate and interleaved stencil, were gen5 and + * gen6. + * + * For a list of all available formats, see the Sandybridge PRM >> Volume + * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface + * Format (p321). + */ + + bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT; + + assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT); + + if (has_stencil) + assert(ISL_DEV_GEN(dev) < 7); + + switch (surf->format) { + default: + unreachable("bad isl depth format"); + case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: + assert(ISL_DEV_GEN(dev) < 7); + return 0; /* D32_FLOAT_S8X24_UINT */ + case ISL_FORMAT_R32_FLOAT: + assert(!has_stencil); + return 1; /* D32_FLOAT */ + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + if (has_stencil) { + assert(ISL_DEV_GEN(dev) < 7); + return 2; /* D24_UNORM_S8_UINT */ + } else { + assert(ISL_DEV_GEN(dev) >= 5); + return 3; /* D24_UNORM_X8_UINT */ + } + case ISL_FORMAT_R16_UNORM: + assert(!has_stencil); + return 5; /* D16_UNORM */ + } +} diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h new file mode 100644 index 00000000000..3e0ff935948 --- /dev/null +++ b/src/intel/isl/isl.h @@ -0,0 +1,1025 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/** + * @file + * @brief Intel Surface Layout + * + * Header Layout + * ------------- + * The header is ordered as: + * - forward declarations + * - macros that may be overridden at compile-time for specific gens + * - enums and constants + * - structs and unions + * - functions + */ + +#pragma once + +#include +#include +#include + +#include "util/macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct brw_device_info; +struct brw_image_param; + +#ifndef ISL_DEV_GEN +/** + * @brief Get the hardware generation of isl_device. + * + * You can define this as a compile-time constant in the CFLAGS. For example, + * `gcc -DISL_DEV_GEN(dev)=9 ...`. + */ +#define ISL_DEV_GEN(__dev) ((__dev)->info->gen) +#endif + +#ifndef ISL_DEV_USE_SEPARATE_STENCIL +/** + * You can define this as a compile-time constant in the CFLAGS. For example, + * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`. + */ +#define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil) +#endif + +/** + * Hardware enumeration SURFACE_FORMAT. + * + * For the official list, see Broadwell PRM: Volume 2b: Command Reference: + * Enumerations: SURFACE_FORMAT. + */ +enum isl_format { + ISL_FORMAT_R32G32B32A32_FLOAT = 0, + ISL_FORMAT_R32G32B32A32_SINT = 1, + ISL_FORMAT_R32G32B32A32_UINT = 2, + ISL_FORMAT_R32G32B32A32_UNORM = 3, + ISL_FORMAT_R32G32B32A32_SNORM = 4, + ISL_FORMAT_R64G64_FLOAT = 5, + ISL_FORMAT_R32G32B32X32_FLOAT = 6, + ISL_FORMAT_R32G32B32A32_SSCALED = 7, + ISL_FORMAT_R32G32B32A32_USCALED = 8, + ISL_FORMAT_R32G32B32A32_SFIXED = 32, + ISL_FORMAT_R64G64_PASSTHRU = 33, + ISL_FORMAT_R32G32B32_FLOAT = 64, + ISL_FORMAT_R32G32B32_SINT = 65, + ISL_FORMAT_R32G32B32_UINT = 66, + ISL_FORMAT_R32G32B32_UNORM = 67, + ISL_FORMAT_R32G32B32_SNORM = 68, + ISL_FORMAT_R32G32B32_SSCALED = 69, + ISL_FORMAT_R32G32B32_USCALED = 70, + ISL_FORMAT_R32G32B32_SFIXED = 80, + ISL_FORMAT_R16G16B16A16_UNORM = 128, + ISL_FORMAT_R16G16B16A16_SNORM = 129, + ISL_FORMAT_R16G16B16A16_SINT = 130, + ISL_FORMAT_R16G16B16A16_UINT = 131, + ISL_FORMAT_R16G16B16A16_FLOAT = 132, + ISL_FORMAT_R32G32_FLOAT = 133, + ISL_FORMAT_R32G32_SINT = 134, + ISL_FORMAT_R32G32_UINT = 135, + ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136, + ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137, + ISL_FORMAT_L32A32_FLOAT = 138, + ISL_FORMAT_R32G32_UNORM = 139, + ISL_FORMAT_R32G32_SNORM = 140, + ISL_FORMAT_R64_FLOAT = 141, + ISL_FORMAT_R16G16B16X16_UNORM = 142, + ISL_FORMAT_R16G16B16X16_FLOAT = 143, + ISL_FORMAT_A32X32_FLOAT = 144, + ISL_FORMAT_L32X32_FLOAT = 145, + ISL_FORMAT_I32X32_FLOAT = 146, + ISL_FORMAT_R16G16B16A16_SSCALED = 147, + ISL_FORMAT_R16G16B16A16_USCALED = 148, + ISL_FORMAT_R32G32_SSCALED = 149, + ISL_FORMAT_R32G32_USCALED = 150, + ISL_FORMAT_R32G32_SFIXED = 160, + ISL_FORMAT_R64_PASSTHRU = 161, + ISL_FORMAT_B8G8R8A8_UNORM = 192, + ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193, + ISL_FORMAT_R10G10B10A2_UNORM = 194, + ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195, + ISL_FORMAT_R10G10B10A2_UINT = 196, + ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197, + ISL_FORMAT_R8G8B8A8_UNORM = 199, + ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200, + ISL_FORMAT_R8G8B8A8_SNORM = 201, + ISL_FORMAT_R8G8B8A8_SINT = 202, + ISL_FORMAT_R8G8B8A8_UINT = 203, + ISL_FORMAT_R16G16_UNORM = 204, + ISL_FORMAT_R16G16_SNORM = 205, + ISL_FORMAT_R16G16_SINT = 206, + ISL_FORMAT_R16G16_UINT = 207, + ISL_FORMAT_R16G16_FLOAT = 208, + ISL_FORMAT_B10G10R10A2_UNORM = 209, + ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210, + ISL_FORMAT_R11G11B10_FLOAT = 211, + ISL_FORMAT_R32_SINT = 214, + ISL_FORMAT_R32_UINT = 215, + ISL_FORMAT_R32_FLOAT = 216, + ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217, + ISL_FORMAT_X24_TYPELESS_G8_UINT = 218, + ISL_FORMAT_L32_UNORM = 221, + ISL_FORMAT_A32_UNORM = 222, + ISL_FORMAT_L16A16_UNORM = 223, + ISL_FORMAT_I24X8_UNORM = 224, + ISL_FORMAT_L24X8_UNORM = 225, + ISL_FORMAT_A24X8_UNORM = 226, + ISL_FORMAT_I32_FLOAT = 227, + ISL_FORMAT_L32_FLOAT = 228, + ISL_FORMAT_A32_FLOAT = 229, + ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230, + ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231, + ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232, + ISL_FORMAT_B8G8R8X8_UNORM = 233, + ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234, + ISL_FORMAT_R8G8B8X8_UNORM = 235, + ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236, + ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237, + ISL_FORMAT_B10G10R10X2_UNORM = 238, + ISL_FORMAT_L16A16_FLOAT = 240, + ISL_FORMAT_R32_UNORM = 241, + ISL_FORMAT_R32_SNORM = 242, + ISL_FORMAT_R10G10B10X2_USCALED = 243, + ISL_FORMAT_R8G8B8A8_SSCALED = 244, + ISL_FORMAT_R8G8B8A8_USCALED = 245, + ISL_FORMAT_R16G16_SSCALED = 246, + ISL_FORMAT_R16G16_USCALED = 247, + ISL_FORMAT_R32_SSCALED = 248, + ISL_FORMAT_R32_USCALED = 249, + ISL_FORMAT_B5G6R5_UNORM = 256, + ISL_FORMAT_B5G6R5_UNORM_SRGB = 257, + ISL_FORMAT_B5G5R5A1_UNORM = 258, + ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259, + ISL_FORMAT_B4G4R4A4_UNORM = 260, + ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261, + ISL_FORMAT_R8G8_UNORM = 262, + ISL_FORMAT_R8G8_SNORM = 263, + ISL_FORMAT_R8G8_SINT = 264, + ISL_FORMAT_R8G8_UINT = 265, + ISL_FORMAT_R16_UNORM = 266, + ISL_FORMAT_R16_SNORM = 267, + ISL_FORMAT_R16_SINT = 268, + ISL_FORMAT_R16_UINT = 269, + ISL_FORMAT_R16_FLOAT = 270, + ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271, + ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272, + ISL_FORMAT_I16_UNORM = 273, + ISL_FORMAT_L16_UNORM = 274, + ISL_FORMAT_A16_UNORM = 275, + ISL_FORMAT_L8A8_UNORM = 276, + ISL_FORMAT_I16_FLOAT = 277, + ISL_FORMAT_L16_FLOAT = 278, + ISL_FORMAT_A16_FLOAT = 279, + ISL_FORMAT_L8A8_UNORM_SRGB = 280, + ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281, + ISL_FORMAT_B5G5R5X1_UNORM = 282, + ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283, + ISL_FORMAT_R8G8_SSCALED = 284, + ISL_FORMAT_R8G8_USCALED = 285, + ISL_FORMAT_R16_SSCALED = 286, + ISL_FORMAT_R16_USCALED = 287, + ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290, + ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291, + ISL_FORMAT_A1B5G5R5_UNORM = 292, + ISL_FORMAT_A4B4G4R4_UNORM = 293, + ISL_FORMAT_L8A8_UINT = 294, + ISL_FORMAT_L8A8_SINT = 295, + ISL_FORMAT_R8_UNORM = 320, + ISL_FORMAT_R8_SNORM = 321, + ISL_FORMAT_R8_SINT = 322, + ISL_FORMAT_R8_UINT = 323, + ISL_FORMAT_A8_UNORM = 324, + ISL_FORMAT_I8_UNORM = 325, + ISL_FORMAT_L8_UNORM = 326, + ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327, + ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328, + ISL_FORMAT_R8_SSCALED = 329, + ISL_FORMAT_R8_USCALED = 330, + ISL_FORMAT_P8_UNORM_PALETTE0 = 331, + ISL_FORMAT_L8_UNORM_SRGB = 332, + ISL_FORMAT_P8_UNORM_PALETTE1 = 333, + ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334, + ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335, + ISL_FORMAT_Y8_UNORM = 336, + ISL_FORMAT_L8_UINT = 338, + ISL_FORMAT_L8_SINT = 339, + ISL_FORMAT_I8_UINT = 340, + ISL_FORMAT_I8_SINT = 341, + ISL_FORMAT_DXT1_RGB_SRGB = 384, + ISL_FORMAT_R1_UNORM = 385, + ISL_FORMAT_YCRCB_NORMAL = 386, + ISL_FORMAT_YCRCB_SWAPUVY = 387, + ISL_FORMAT_P2_UNORM_PALETTE0 = 388, + ISL_FORMAT_P2_UNORM_PALETTE1 = 389, + ISL_FORMAT_BC1_UNORM = 390, + ISL_FORMAT_BC2_UNORM = 391, + ISL_FORMAT_BC3_UNORM = 392, + ISL_FORMAT_BC4_UNORM = 393, + ISL_FORMAT_BC5_UNORM = 394, + ISL_FORMAT_BC1_UNORM_SRGB = 395, + ISL_FORMAT_BC2_UNORM_SRGB = 396, + ISL_FORMAT_BC3_UNORM_SRGB = 397, + ISL_FORMAT_MONO8 = 398, + ISL_FORMAT_YCRCB_SWAPUV = 399, + ISL_FORMAT_YCRCB_SWAPY = 400, + ISL_FORMAT_DXT1_RGB = 401, + ISL_FORMAT_FXT1 = 402, + ISL_FORMAT_R8G8B8_UNORM = 403, + ISL_FORMAT_R8G8B8_SNORM = 404, + ISL_FORMAT_R8G8B8_SSCALED = 405, + ISL_FORMAT_R8G8B8_USCALED = 406, + ISL_FORMAT_R64G64B64A64_FLOAT = 407, + ISL_FORMAT_R64G64B64_FLOAT = 408, + ISL_FORMAT_BC4_SNORM = 409, + ISL_FORMAT_BC5_SNORM = 410, + ISL_FORMAT_R16G16B16_FLOAT = 411, + ISL_FORMAT_R16G16B16_UNORM = 412, + ISL_FORMAT_R16G16B16_SNORM = 413, + ISL_FORMAT_R16G16B16_SSCALED = 414, + ISL_FORMAT_R16G16B16_USCALED = 415, + ISL_FORMAT_BC6H_SF16 = 417, + ISL_FORMAT_BC7_UNORM = 418, + ISL_FORMAT_BC7_UNORM_SRGB = 419, + ISL_FORMAT_BC6H_UF16 = 420, + ISL_FORMAT_PLANAR_420_8 = 421, + ISL_FORMAT_R8G8B8_UNORM_SRGB = 424, + ISL_FORMAT_ETC1_RGB8 = 425, + ISL_FORMAT_ETC2_RGB8 = 426, + ISL_FORMAT_EAC_R11 = 427, + ISL_FORMAT_EAC_RG11 = 428, + ISL_FORMAT_EAC_SIGNED_R11 = 429, + ISL_FORMAT_EAC_SIGNED_RG11 = 430, + ISL_FORMAT_ETC2_SRGB8 = 431, + ISL_FORMAT_R16G16B16_UINT = 432, + ISL_FORMAT_R16G16B16_SINT = 433, + ISL_FORMAT_R32_SFIXED = 434, + ISL_FORMAT_R10G10B10A2_SNORM = 435, + ISL_FORMAT_R10G10B10A2_USCALED = 436, + ISL_FORMAT_R10G10B10A2_SSCALED = 437, + ISL_FORMAT_R10G10B10A2_SINT = 438, + ISL_FORMAT_B10G10R10A2_SNORM = 439, + ISL_FORMAT_B10G10R10A2_USCALED = 440, + ISL_FORMAT_B10G10R10A2_SSCALED = 441, + ISL_FORMAT_B10G10R10A2_UINT = 442, + ISL_FORMAT_B10G10R10A2_SINT = 443, + ISL_FORMAT_R64G64B64A64_PASSTHRU = 444, + ISL_FORMAT_R64G64B64_PASSTHRU = 445, + ISL_FORMAT_ETC2_RGB8_PTA = 448, + ISL_FORMAT_ETC2_SRGB8_PTA = 449, + ISL_FORMAT_ETC2_EAC_RGBA8 = 450, + ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451, + ISL_FORMAT_R8G8B8_UINT = 456, + ISL_FORMAT_R8G8B8_SINT = 457, + ISL_FORMAT_RAW = 511, + + /* Hardware doesn't understand this out-of-band value */ + ISL_FORMAT_UNSUPPORTED = UINT16_MAX, +}; + +/** + * Numerical base type for channels of isl_format. + */ +enum isl_base_type { + ISL_VOID, + ISL_RAW, + ISL_UNORM, + ISL_SNORM, + ISL_UFLOAT, + ISL_SFLOAT, + ISL_UFIXED, + ISL_SFIXED, + ISL_UINT, + ISL_SINT, + ISL_USCALED, + ISL_SSCALED, +}; + +/** + * Colorspace of isl_format. + */ +enum isl_colorspace { + ISL_COLORSPACE_NONE = 0, + ISL_COLORSPACE_LINEAR, + ISL_COLORSPACE_SRGB, + ISL_COLORSPACE_YUV, +}; + +/** + * Texture compression mode of isl_format. + */ +enum isl_txc { + ISL_TXC_NONE = 0, + ISL_TXC_DXT1, + ISL_TXC_DXT3, + ISL_TXC_DXT5, + ISL_TXC_FXT1, + ISL_TXC_RGTC1, + ISL_TXC_RGTC2, + ISL_TXC_BPTC, + ISL_TXC_ETC1, + ISL_TXC_ETC2, +}; + +/** + * @brief Hardware tile mode + * + * WARNING: These values differ from the hardware enum values, which are + * unstable across hardware generations. + * + * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to + * clearly distinguish it from Yf and Ys. + */ +enum isl_tiling { + ISL_TILING_LINEAR = 0, + ISL_TILING_W, + ISL_TILING_X, + ISL_TILING_Y0, /**< Legacy Y tiling */ + ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ + ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ +}; + +/** + * @defgroup Tiling Flags + * @{ + */ +typedef uint32_t isl_tiling_flags_t; +#define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR) +#define ISL_TILING_W_BIT (1u << ISL_TILING_W) +#define ISL_TILING_X_BIT (1u << ISL_TILING_X) +#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0) +#define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf) +#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) +#define ISL_TILING_ANY_MASK (~0u) +#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) + +/** Any Y tiling, including legacy Y tiling. */ +#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \ + ISL_TILING_Yf_BIT | \ + ISL_TILING_Ys_BIT) + +/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */ +#define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \ + ISL_TILING_Ys_BIT) +/** @} */ + +/** + * @brief Logical dimension of surface. + * + * Note: There is no dimension for cube map surfaces. ISL interprets cube maps + * as 2D array surfaces. + */ +enum isl_surf_dim { + ISL_SURF_DIM_1D, + ISL_SURF_DIM_2D, + ISL_SURF_DIM_3D, +}; + +/** + * @brief Physical layout of the surface's dimensions. + */ +enum isl_dim_layout { + /** + * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section + * 6.17.3: 2D Surfaces. + * + * On many gens, 1D surfaces share the same layout as 2D surfaces. From + * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces: + * + * One-dimensional surfaces are identical to 2D surfaces with height of + * one. + * + * @invariant isl_surf::phys_level0_sa::depth == 1 + */ + ISL_DIM_LAYOUT_GEN4_2D, + + /** + * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section + * 6.17.5: 3D Surfaces. + * + * @invariant isl_surf::phys_level0_sa::array_len == 1 + */ + ISL_DIM_LAYOUT_GEN4_3D, + + /** + * For details, see the Skylake BSpec >> Memory Views >> Common Surface + * Formats >> Surface Layout and Tiling >> » 1D Surfaces. + */ + ISL_DIM_LAYOUT_GEN9_1D, +}; + +/* TODO(chadv): Explain */ +enum isl_array_pitch_span { + ISL_ARRAY_PITCH_SPAN_FULL, + ISL_ARRAY_PITCH_SPAN_COMPACT, +}; + +/** + * @defgroup Surface Usage + * @{ + */ +typedef uint64_t isl_surf_usage_flags_t; +#define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0) +#define ISL_SURF_USAGE_DEPTH_BIT (1u << 1) +#define ISL_SURF_USAGE_STENCIL_BIT (1u << 2) +#define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3) +#define ISL_SURF_USAGE_CUBE_BIT (1u << 4) +#define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5) +#define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9) +#define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10) +#define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11) +/** @} */ + +/** + * Identical to VkSampleCountFlagBits. + */ +enum isl_sample_count { + ISL_SAMPLE_COUNT_1_BIT = 1u, + ISL_SAMPLE_COUNT_2_BIT = 2u, + ISL_SAMPLE_COUNT_4_BIT = 4u, + ISL_SAMPLE_COUNT_8_BIT = 8u, + ISL_SAMPLE_COUNT_16_BIT = 16u, +}; +typedef uint32_t isl_sample_count_mask_t; + +/** + * @brief Multisample Format + */ +enum isl_msaa_layout { + /** + * @brief Suface is single-sampled. + */ + ISL_MSAA_LAYOUT_NONE, + + /** + * @brief [SNB+] Interleaved Multisample Format + * + * In this format, multiple samples are interleaved into each cacheline. + * In other words, the sample index is swizzled into the low 6 bits of the + * surface's virtual address space. + * + * For example, suppose the surface is legacy Y tiled, is 4x multisampled, + * and its pixel format is 32bpp. Then the first cacheline is arranged + * thus: + * + * (0,0,0) (0,1,0) (0,0,1) (1,0,1) + * (1,0,0) (1,1,0) (0,1,1) (1,1,1) + * + * (0,0,2) (1,0,2) (0,0,3) (1,0,3) + * (0,1,2) (1,1,2) (0,1,3) (1,1,3) + * + * The hardware docs refer to this format with multiple terms. In + * Sandybridge, this is the only multisample format; so no term is used. + * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved + * Multisample Surface). Later hardware docs additionally refer to this + * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for + * color surfaces). + * + * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled + * Surface Behavior". + * + * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved + * Multisampled Surfaces". + */ + ISL_MSAA_LAYOUT_INTERLEAVED, + + /** + * @brief [IVB+] Array Multisample Format + * + * In this format, the surface's physical layout resembles that of a + * 2D array surface. + * + * Suppose the multisample surface's logical extent is (w, h) and its + * sample count is N. Then surface's physical extent is the same as + * a singlesample 2D surface whose logical extent is (w, h) and array + * length is N. Array slice `i` contains the pixel values for sample + * index `i`. + * + * The Ivybridge docs refer to surfaces in this format as UMS + * (Uncompressed Multsample Layout) and CMS (Compressed Multisample + * Surface). The Broadwell docs additionally refer to this format as + * MSFMT_MSS (MSS=Multisample Surface Storage). + * + * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed + * Multisample Surfaces". + * + * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed + * Multisample Surfaces". + */ + ISL_MSAA_LAYOUT_ARRAY, +}; + + +struct isl_device { + const struct brw_device_info *info; + bool use_separate_stencil; + bool has_bit6_swizzling; +}; + +struct isl_extent2d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; +}; + +struct isl_extent3d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; + union { uint32_t d, depth; }; +}; + +struct isl_extent4d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; + union { uint32_t d, depth; }; + union { uint32_t a, array_len; }; +}; + +struct isl_channel_layout { + enum isl_base_type type; + uint8_t bits; /**< Size in bits */ +}; + +/** + * Each format has 3D block extent (width, height, depth). The block extent of + * compressed formats is that of the format's compression block. For example, + * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block + * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is + * is (w=1, h=1, d=1). + */ +struct isl_format_layout { + enum isl_format format; + + uint8_t bs; /**< Block size, in bytes, rounded towards 0 */ + uint8_t bw; /**< Block width, in pixels */ + uint8_t bh; /**< Block height, in pixels */ + uint8_t bd; /**< Block depth, in pixels */ + + struct { + struct isl_channel_layout r; /**< Red channel */ + struct isl_channel_layout g; /**< Green channel */ + struct isl_channel_layout b; /**< Blue channel */ + struct isl_channel_layout a; /**< Alpha channel */ + struct isl_channel_layout l; /**< Luminance channel */ + struct isl_channel_layout i; /**< Intensity channel */ + struct isl_channel_layout p; /**< Palette channel */ + } channels; + + enum isl_colorspace colorspace; + enum isl_txc txc; +}; + +struct isl_tile_info { + enum isl_tiling tiling; + uint32_t width; /**< in bytes */ + uint32_t height; /**< in rows of memory */ + uint32_t size; /**< in bytes */ +}; + +/** + * @brief Input to surface initialization + * + * @invariant width >= 1 + * @invariant height >= 1 + * @invariant depth >= 1 + * @invariant levels >= 1 + * @invariant samples >= 1 + * @invariant array_len >= 1 + * + * @invariant if 1D then height == 1 and depth == 1 and samples == 1 + * @invariant if 2D then depth == 1 + * @invariant if 3D then array_len == 1 and samples == 1 + */ +struct isl_surf_init_info { + enum isl_surf_dim dim; + enum isl_format format; + + uint32_t width; + uint32_t height; + uint32_t depth; + uint32_t levels; + uint32_t array_len; + uint32_t samples; + + /** Lower bound for isl_surf::alignment, in bytes. */ + uint32_t min_alignment; + + /** Lower bound for isl_surf::pitch, in bytes. */ + uint32_t min_pitch; + + isl_surf_usage_flags_t usage; + + /** Flags that alter how ISL selects isl_surf::tiling. */ + isl_tiling_flags_t tiling_flags; +}; + +struct isl_surf { + enum isl_surf_dim dim; + enum isl_dim_layout dim_layout; + enum isl_msaa_layout msaa_layout; + enum isl_tiling tiling; + enum isl_format format; + + /** + * Alignment of the upper-left sample of each subimage, in units of surface + * elements. + */ + struct isl_extent3d image_alignment_el; + + /** + * Logical extent of the surface's base level, in units of pixels. This is + * identical to the extent defined in isl_surf_init_info. + */ + struct isl_extent4d logical_level0_px; + + /** + * Physical extent of the surface's base level, in units of physical + * surface samples and aligned to the format's compression block. + * + * Consider isl_dim_layout as an operator that transforms a logical surface + * layout to a physical surface layout. Then + * + * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px) + * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout + */ + struct isl_extent4d phys_level0_sa; + + uint32_t levels; + uint32_t samples; + + /** Total size of the surface, in bytes. */ + uint32_t size; + + /** Required alignment for the surface's base address. */ + uint32_t alignment; + + /** + * Pitch between vertically adjacent surface elements, in bytes. + */ + uint32_t row_pitch; + + /** + * Pitch between physical array slices, in rows of surface elements. + */ + uint32_t array_pitch_el_rows; + + enum isl_array_pitch_span array_pitch_span; + + /** Copy of isl_surf_init_info::usage. */ + isl_surf_usage_flags_t usage; +}; + +extern const struct isl_format_layout isl_format_layouts[]; + +void +isl_device_init(struct isl_device *dev, + const struct brw_device_info *info, + bool has_bit6_swizzling); + +isl_sample_count_mask_t ATTRIBUTE_CONST +isl_device_get_sample_counts(struct isl_device *dev); + +static inline const struct isl_format_layout * ATTRIBUTE_CONST +isl_format_get_layout(enum isl_format fmt) +{ + return &isl_format_layouts[fmt]; +} + +bool +isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST; + +static inline bool +isl_format_is_compressed(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->txc != ISL_TXC_NONE; +} + +static inline bool +isl_format_has_bc_compression(enum isl_format fmt) +{ + switch (isl_format_get_layout(fmt)->txc) { + case ISL_TXC_DXT1: + case ISL_TXC_DXT3: + case ISL_TXC_DXT5: + return true; + case ISL_TXC_NONE: + case ISL_TXC_FXT1: + case ISL_TXC_RGTC1: + case ISL_TXC_RGTC2: + case ISL_TXC_BPTC: + case ISL_TXC_ETC1: + case ISL_TXC_ETC2: + return false; + } + + unreachable("bad texture compression mode"); + return false; +} + +static inline bool +isl_format_is_yuv(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->colorspace == ISL_COLORSPACE_YUV; +} + +static inline bool +isl_format_block_is_1x1x1(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1; +} + +static inline bool +isl_format_is_rgb(enum isl_format fmt) +{ + return isl_format_layouts[fmt].channels.r.bits > 0 && + isl_format_layouts[fmt].channels.g.bits > 0 && + isl_format_layouts[fmt].channels.b.bits > 0 && + isl_format_layouts[fmt].channels.a.bits == 0; +} + +enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; +enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST; + +bool isl_is_storage_image_format(enum isl_format fmt); + +enum isl_format +isl_lower_storage_image_format(const struct isl_device *dev, + enum isl_format fmt); + +static inline bool +isl_tiling_is_any_y(enum isl_tiling tiling) +{ + return (1u << tiling) & ISL_TILING_ANY_MASK; +} + +static inline bool +isl_tiling_is_std_y(enum isl_tiling tiling) +{ + return (1u << tiling) & ISL_TILING_STD_Y_MASK; +} + +bool +isl_tiling_get_info(const struct isl_device *dev, + enum isl_tiling tiling, + uint32_t format_block_size, + struct isl_tile_info *info); + +void +isl_tiling_get_extent(const struct isl_device *dev, + enum isl_tiling tiling, + uint32_t format_block_size, + struct isl_extent2d *e); +bool +isl_surf_choose_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling *tiling); + +static inline bool +isl_surf_usage_is_display(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_DISPLAY_BIT; +} + +static inline bool +isl_surf_usage_is_depth(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_DEPTH_BIT; +} + +static inline bool +isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_STENCIL_BIT; +} + +static inline bool +isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage) +{ + return (usage & ISL_SURF_USAGE_DEPTH_BIT) && + (usage & ISL_SURF_USAGE_STENCIL_BIT); +} + +static inline bool +isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage) +{ + return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT); +} + +static inline bool +isl_surf_info_is_z16(const struct isl_surf_init_info *info) +{ + return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && + (info->format == ISL_FORMAT_R16_UNORM); +} + +static inline bool +isl_surf_info_is_z32_float(const struct isl_surf_init_info *info) +{ + return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && + (info->format == ISL_FORMAT_R32_FLOAT); +} + +static inline struct isl_extent2d +isl_extent2d(uint32_t width, uint32_t height) +{ + return (struct isl_extent2d) { .w = width, .h = height }; +} + +static inline struct isl_extent3d +isl_extent3d(uint32_t width, uint32_t height, uint32_t depth) +{ + return (struct isl_extent3d) { .w = width, .h = height, .d = depth }; +} + +static inline struct isl_extent4d +isl_extent4d(uint32_t width, uint32_t height, uint32_t depth, + uint32_t array_len) +{ + return (struct isl_extent4d) { + .w = width, + .h = height, + .d = depth, + .a = array_len, + }; +} + +#define isl_surf_init(dev, surf, ...) \ + isl_surf_init_s((dev), (surf), \ + &(struct isl_surf_init_info) { __VA_ARGS__ }); + +bool +isl_surf_init_s(const struct isl_device *dev, + struct isl_surf *surf, + const struct isl_surf_init_info *restrict info); + +void +isl_surf_get_tile_info(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_tile_info *tile_info); + +/** + * Alignment of the upper-left sample of each subimage, in units of surface + * elements. + */ +static inline struct isl_extent3d +isl_surf_get_image_alignment_el(const struct isl_surf *surf) +{ + return surf->image_alignment_el; +} + +/** + * Alignment of the upper-left sample of each subimage, in units of surface + * samples. + */ +static inline struct isl_extent3d +isl_surf_get_image_alignment_sa(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + return (struct isl_extent3d) { + .w = fmtl->bw * surf->image_alignment_el.w, + .h = fmtl->bh * surf->image_alignment_el.h, + .d = fmtl->bd * surf->image_alignment_el.d, + }; +} + +/** + * Pitch between vertically adjacent surface elements, in bytes. + */ +static inline uint32_t +isl_surf_get_row_pitch(const struct isl_surf *surf) +{ + return surf->row_pitch; +} + +/** + * Pitch between vertically adjacent surface elements, in units of surface elements. + */ +static inline uint32_t +isl_surf_get_row_pitch_el(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + assert(surf->row_pitch % fmtl->bs == 0); + return surf->row_pitch / fmtl->bs; +} + +/** + * Pitch between physical array slices, in rows of surface elements. + */ +static inline uint32_t +isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf) +{ + return surf->array_pitch_el_rows; +} + +/** + * Pitch between physical array slices, in units of surface elements. + */ +static inline uint32_t +isl_surf_get_array_pitch_el(const struct isl_surf *surf) +{ + return isl_surf_get_array_pitch_el_rows(surf) * + isl_surf_get_row_pitch_el(surf); +} + +/** + * Pitch between physical array slices, in rows of surface samples. + */ +static inline uint32_t +isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf); +} + +/** + * Pitch between physical array slices, in bytes. + */ +static inline uint32_t +isl_surf_get_array_pitch(const struct isl_surf *surf) +{ + return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; +} + +/** + * Calculate the offset, in units of surface elements, to a subimage in the + * surface. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +void +isl_surf_get_image_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_el, + uint32_t *y_offset_el); + +/** + * @brief Calculate the intratile offsets to a subimage in the surface. + * + * In @a base_address_offset return the offset from the base of the surface to + * the base address of the first tile of the subimage. In @a x_offset_el and + * @a y_offset_el, return the offset, in units of surface elements, from the + * tile's base to the subimage's first surface element. The x and y offsets + * are intratile offsets; that is, they do not exceed the boundary of the + * surface's tiling format. + */ +void +isl_surf_get_image_intratile_offset_el(const struct isl_device *dev, + const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset, + uint32_t *base_address_offset, + uint32_t *x_offset_el, + uint32_t *y_offset_el); + +/** + * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat + * + * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT + * @pre surf->format must be a valid format for depth surfaces + */ +uint32_t +isl_surf_get_depth_format(const struct isl_device *dev, + const struct isl_surf *surf); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c new file mode 100644 index 00000000000..0fe6e9b83ab --- /dev/null +++ b/src/intel/isl/isl_format.c @@ -0,0 +1,95 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include + +#include "isl.h" + +bool +isl_format_has_sint_channel(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->channels.r.type == ISL_SINT || + fmtl->channels.g.type == ISL_SINT || + fmtl->channels.b.type == ISL_SINT || + fmtl->channels.a.type == ISL_SINT || + fmtl->channels.l.type == ISL_SINT || + fmtl->channels.i.type == ISL_SINT || + fmtl->channels.p.type == ISL_SINT || + fmtl->channels.g.type == ISL_SINT; +} + +enum isl_format +isl_format_rgb_to_rgba(enum isl_format rgb) +{ + assert(isl_format_is_rgb(rgb)); + + switch (rgb) { + case ISL_FORMAT_R32G32B32_FLOAT: return ISL_FORMAT_R32G32B32A32_FLOAT; + case ISL_FORMAT_R32G32B32_SINT: return ISL_FORMAT_R32G32B32A32_SINT; + case ISL_FORMAT_R32G32B32_UINT: return ISL_FORMAT_R32G32B32A32_UINT; + case ISL_FORMAT_R32G32B32_UNORM: return ISL_FORMAT_R32G32B32A32_UNORM; + case ISL_FORMAT_R32G32B32_SNORM: return ISL_FORMAT_R32G32B32A32_SNORM; + case ISL_FORMAT_R32G32B32_SSCALED: return ISL_FORMAT_R32G32B32A32_SSCALED; + case ISL_FORMAT_R32G32B32_USCALED: return ISL_FORMAT_R32G32B32A32_USCALED; + case ISL_FORMAT_R32G32B32_SFIXED: return ISL_FORMAT_R32G32B32A32_SFIXED; + case ISL_FORMAT_R8G8B8_UNORM: return ISL_FORMAT_R8G8B8A8_UNORM; + case ISL_FORMAT_R8G8B8_SNORM: return ISL_FORMAT_R8G8B8A8_SNORM; + case ISL_FORMAT_R8G8B8_SSCALED: return ISL_FORMAT_R8G8B8A8_SSCALED; + case ISL_FORMAT_R8G8B8_USCALED: return ISL_FORMAT_R8G8B8A8_USCALED; + case ISL_FORMAT_R16G16B16_FLOAT: return ISL_FORMAT_R16G16B16A16_FLOAT; + case ISL_FORMAT_R16G16B16_UNORM: return ISL_FORMAT_R16G16B16A16_UNORM; + case ISL_FORMAT_R16G16B16_SNORM: return ISL_FORMAT_R16G16B16A16_SNORM; + case ISL_FORMAT_R16G16B16_SSCALED: return ISL_FORMAT_R16G16B16A16_SSCALED; + case ISL_FORMAT_R16G16B16_USCALED: return ISL_FORMAT_R16G16B16A16_USCALED; + case ISL_FORMAT_R8G8B8_UNORM_SRGB: return ISL_FORMAT_R8G8B8A8_UNORM_SRGB; + case ISL_FORMAT_R16G16B16_UINT: return ISL_FORMAT_R16G16B16A16_UINT; + case ISL_FORMAT_R16G16B16_SINT: return ISL_FORMAT_R16G16B16A16_SINT; + case ISL_FORMAT_R8G8B8_UINT: return ISL_FORMAT_R8G8B8A8_UINT; + case ISL_FORMAT_R8G8B8_SINT: return ISL_FORMAT_R8G8B8A8_SINT; + default: + return ISL_FORMAT_UNSUPPORTED; + } +} + +enum isl_format +isl_format_rgb_to_rgbx(enum isl_format rgb) +{ + assert(isl_format_is_rgb(rgb)); + + switch (rgb) { + case ISL_FORMAT_R32G32B32_FLOAT: + return ISL_FORMAT_R32G32B32X32_FLOAT; + case ISL_FORMAT_R16G16B16_UNORM: + return ISL_FORMAT_R16G16B16X16_UNORM; + case ISL_FORMAT_R16G16B16_FLOAT: + return ISL_FORMAT_R16G16B16X16_FLOAT; + case ISL_FORMAT_R8G8B8_UNORM: + return ISL_FORMAT_R8G8B8X8_UNORM; + case ISL_FORMAT_R8G8B8_UNORM_SRGB: + return ISL_FORMAT_R8G8B8X8_UNORM_SRGB; + default: + return ISL_FORMAT_UNSUPPORTED; + } +} diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv new file mode 100644 index 00000000000..af2786ae630 --- /dev/null +++ b/src/intel/isl/isl_format_layout.csv @@ -0,0 +1,287 @@ +# Copyright 2015 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +# +# @file +# @brief Layout of all hardware surface formats +# +# For the official list, see Broadwell PRM: Volume 2b: Command Reference: +# Enumerations: SURFACE_FORMAT. +# + + +# Columns: +# name: format name in PRM +# bpb: bits per block +# bw: block width, in pixels +# bh: block height, in pixels +# bd: block depth, in pixels +# r: red channel, data type and bitwidth +# g: green channel +# b: blue channel +# a: alpha channel +# l: luminance channel +# i: intensity channel +# p: palette channel +# space: colorspace +# txc: texture compression +# +# Data Types: +# x: void +# r: raw +# un: unorm +# sn: snorm +# uf: ufloat +# sf: sfloat +# ux: ufixed +# sx: sfixed +# ui: uint +# si: sint +# us: uscaled +# ss: sscaled + + +# Table is aligned with the Vim commands below, using the Align plugin: +# :AlignCtrl lr+ p8000000000000P1 +# /^# name/,$ Align, + +# name , bpb, bw, bh, bd, r, g, b, a, l, i, p, space, txc +R32G32B32A32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, sf32, , , , linear, +R32G32B32A32_SINT , 128, 1, 1, 1, si32, si32, si32, si32, , , , linear, +R32G32B32A32_UINT , 128, 1, 1, 1, ui32, ui32, ui32, ui32, , , , linear, +R32G32B32A32_UNORM , 128, 1, 1, 1, un32, un32, un32, un32, , , , linear, +R32G32B32A32_SNORM , 128, 1, 1, 1, sn32, sn32, sn32, sn32, , , , linear, +R64G64_FLOAT , 128, 1, 1, 1, sf64, sf64, , , , , , linear, +R32G32B32X32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, x32, , , , linear, +R32G32B32A32_SSCALED , 128, 1, 1, 1, ss32, ss32, ss32, ss32, , , , linear, +R32G32B32A32_USCALED , 128, 1, 1, 1, us32, us32, us32, us32, , , , linear, +R32G32B32A32_SFIXED , 128, 1, 1, 1, sx32, sx32, sx32, sx32, , , , linear, +R64G64_PASSTHRU , 128, 1, 1, 1, r64, r64, , , , , , , +R32G32B32_FLOAT , 96, 1, 1, 1, sf32, sf32, sf32, , , , , linear, +R32G32B32_SINT , 96, 1, 1, 1, si32, si32, si32, , , , , linear, +R32G32B32_UINT , 96, 1, 1, 1, ui32, ui32, ui32, , , , , linear, +R32G32B32_UNORM , 96, 1, 1, 1, un32, un32, un32, , , , , linear, +R32G32B32_SNORM , 96, 1, 1, 1, sn32, sn32, sn32, , , , , linear, +R32G32B32_SSCALED , 96, 1, 1, 1, ss32, ss32, ss32, , , , , linear, +R32G32B32_USCALED , 96, 1, 1, 1, us32, us32, us32, , , , , linear, +R32G32B32_SFIXED , 96, 1, 1, 1, sx32, sx32, sx32, , , , , linear, +R16G16B16A16_UNORM , 64, 1, 1, 1, un16, un16, un16, un16, , , , linear, +R16G16B16A16_SNORM , 64, 1, 1, 1, sn16, sn16, sn16, sn16, , , , linear, +R16G16B16A16_SINT , 64, 1, 1, 1, si16, si16, si16, si16, , , , linear, +R16G16B16A16_UINT , 64, 1, 1, 1, ui16, ui16, ui16, ui16, , , , linear, +R16G16B16A16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, sf16, , , , linear, +R32G32_FLOAT , 64, 1, 1, 1, sf32, sf32, , , , , , linear, +R32G32_SINT , 64, 1, 1, 1, si32, si32, , , , , , linear, +R32G32_UINT , 64, 1, 1, 1, ui32, ui32, , , , , , linear, +R32_FLOAT_X8X24_TYPELESS , 64, 1, 1, 1, sf32, x8, x24, , , , , linear, +X32_TYPELESS_G8X24_UINT , 64, 1, 1, 1, x32, ui8, x24, , , , , linear, +L32A32_FLOAT , 64, 1, 1, 1, , , , sf32, sf32, , , linear, +R32G32_UNORM , 64, 1, 1, 1, un32, un32, , , , , , linear, +R32G32_SNORM , 64, 1, 1, 1, sn32, sn32, , , , , , linear, +R64_FLOAT , 64, 1, 1, 1, sf64, , , , , , , linear, +R16G16B16X16_UNORM , 64, 1, 1, 1, un16, un16, un16, x16, , , , linear, +R16G16B16X16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, x16, , , , linear, +A32X32_FLOAT , 64, 1, 1, 1, , , , sf32, x32, , , alpha, +L32X32_FLOAT , 64, 1, 1, 1, , , , x32, sf32, , , linear, +I32X32_FLOAT , 64, 1, 1, 1, , , , x32, , sf32, , linear, +R16G16B16A16_SSCALED , 64, 1, 1, 1, ss16, ss16, ss16, ss16, , , , linear, +R16G16B16A16_USCALED , 64, 1, 1, 1, us16, us16, us16, us16, , , , linear, +R32G32_SSCALED , 64, 1, 1, 1, ss32, ss32, , , , , , linear, +R32G32_USCALED , 64, 1, 1, 1, us32, us32, , , , , , linear, +R32G32_SFIXED , 64, 1, 1, 1, sx32, sx32, , , , , , linear, +R64_PASSTHRU , 64, 1, 1, 1, r64, , , , , , , , +B8G8R8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, +B8G8R8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, +R10G10B10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, +R10G10B10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, +R10G10B10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, +R10G10B10_SNORM_A2_UNORM , 32, 1, 1, 1, sn10, sn10, sn10, un2, , , , linear, +R8G8B8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, +R8G8B8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, +R8G8B8A8_SNORM , 32, 1, 1, 1, sn8, sn8, sn8, sn8, , , , linear, +R8G8B8A8_SINT , 32, 1, 1, 1, si8, si8, si8, si8, , , , linear, +R8G8B8A8_UINT , 32, 1, 1, 1, ui8, ui8, ui8, ui8, , , , linear, +R16G16_UNORM , 32, 1, 1, 1, un16, un16, , , , , , linear, +R16G16_SNORM , 32, 1, 1, 1, sn16, sn16, , , , , , linear, +R16G16_SINT , 32, 1, 1, 1, si16, si16, , , , , , linear, +R16G16_UINT , 32, 1, 1, 1, ui16, ui16, , , , , , linear, +R16G16_FLOAT , 32, 1, 1, 1, sf16, sf16, , , , , , linear, +B10G10R10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, +B10G10R10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, +R11G11B10_FLOAT , 32, 1, 1, 1, uf11, uf11, uf10, , , , , linear, +R32_SINT , 32, 1, 1, 1, si32, , , , , , , linear, +R32_UINT , 32, 1, 1, 1, ui32, , , , , , , linear, +R32_FLOAT , 32, 1, 1, 1, sf32, , , , , , , linear, +R24_UNORM_X8_TYPELESS , 32, 1, 1, 1, un24, x8, , , , , , linear, +X24_TYPELESS_G8_UINT , 32, 1, 1, 1, x24, ui8, , , , , , linear, +L32_UNORM , 32, 1, 1, 1, , , , , un32, , , linear, +A32_UNORM , 32, 1, 1, 1, , , , un32, , , , alpha, +L16A16_UNORM , 32, 1, 1, 1, , , , un16, un16, , , linear, +I24X8_UNORM , 32, 1, 1, 1, , , , x8, , un24, , linear, +L24X8_UNORM , 32, 1, 1, 1, , , , x8, un24, , , linear, +A24X8_UNORM , 32, 1, 1, 1, , , , un24, x8, , , alpha, +I32_FLOAT , 32, 1, 1, 1, , , , , , sf32, , linear, +L32_FLOAT , 32, 1, 1, 1, , , , , sf32, , , linear, +A32_FLOAT , 32, 1, 1, 1, , , , sf32, , , , alpha, +X8B8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, +A8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, x8, un8, , , , linear, +B8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, +B8G8R8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, +B8G8R8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, +R8G8B8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, +R8G8B8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, +R9G9B9E5_SHAREDEXP , 32, 1, 1, 1, ui9, ui9, ui9, , , , , linear, +B10G10R10X2_UNORM , 32, 1, 1, 1, un10, un10, un10, x2, , , , linear, +L16A16_FLOAT , 32, 1, 1, 1, , , , sf16, sf16, , , linear, +R32_UNORM , 32, 1, 1, 1, un32, , , , , , , linear, +R32_SNORM , 32, 1, 1, 1, sn32, , , , , , , linear, +R10G10B10X2_USCALED , 32, 1, 1, 1, us10, us10, us10, x2, , , , linear, +R8G8B8A8_SSCALED , 32, 1, 1, 1, ss8, ss8, ss8, ss8, , , , linear, +R8G8B8A8_USCALED , 32, 1, 1, 1, us8, us8, us8, us8, , , , linear, +R16G16_SSCALED , 32, 1, 1, 1, ss16, ss6, , , , , , linear, +R16G16_USCALED , 32, 1, 1, 1, us16, us16, , , , , , linear, +R32_SSCALED , 32, 1, 1, 1, ss32, , , , , , , linear, +R32_USCALED , 32, 1, 1, 1, us32, , , , , , , linear, +B5G6R5_UNORM , 16, 1, 1, 1, un5, un6, un5, , , , , linear, +B5G6R5_UNORM_SRGB , 16, 1, 1, 1, un5, un6, un5, , , , , srgb, +B5G5R5A1_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, +B5G5R5A1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, un1, , , , srgb, +B4G4R4A4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, +B4G4R4A4_UNORM_SRGB , 16, 1, 1, 1, un4, un4, un4, un4, , , , srgb, +R8G8_UNORM , 16, 1, 1, 1, un8, un8, , , , , , linear, +R8G8_SNORM , 16, 1, 1, 1, sn8, sn8, , , , , , linear, +R8G8_SINT , 16, 1, 1, 1, si8, si8, , , , , , linear, +R8G8_UINT , 16, 1, 1, 1, ui8, ui8, , , , , , linear, +R16_UNORM , 16, 1, 1, 1, un16, , , , , , , linear, +R16_SNORM , 16, 1, 1, 1, sn16, , , , , , , linear, +R16_SINT , 16, 1, 1, 1, si16, , , , , , , linear, +R16_UINT , 16, 1, 1, 1, ui16, , , , , , , linear, +R16_FLOAT , 16, 1, 1, 1, sf16, , , , , , , linear, +A8P8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, +A8P8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, +I16_UNORM , 16, 1, 1, 1, , , , , , un16, , linear, +L16_UNORM , 16, 1, 1, 1, , , , , un16, , , linear, +A16_UNORM , 16, 1, 1, 1, , , , un16, , , , alpha, +L8A8_UNORM , 16, 1, 1, 1, , , , un8, un8, , , linear, +I16_FLOAT , 16, 1, 1, 1, , , , , , sf16, , linear, +L16_FLOAT , 16, 1, 1, 1, , , , , sf16, , , linear, +A16_FLOAT , 16, 1, 1, 1, , , , sf16, , , , alpha, +L8A8_UNORM_SRGB , 16, 1, 1, 1, , , , un8, un8, , , srgb, +R5G5_SNORM_B6_UNORM , 16, 1, 1, 1, sn5, sn5, un6, , , , , linear, +B5G5R5X1_UNORM , 16, 1, 1, 1, un5, un5, un5, x1, , , , linear, +B5G5R5X1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, x1, , , , srgb, +R8G8_SSCALED , 16, 1, 1, 1, ss8, ss8, , , , , , linear, +R8G8_USCALED , 16, 1, 1, 1, us8, us8, , , , , , linear, +R16_SSCALED , 16, 1, 1, 1, ss16, , , , , , , linear, +R16_USCALED , 16, 1, 1, 1, us16, , , , , , , linear, +P8A8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, +P8A8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, +A1B5G5R5_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, +A4B4G4R4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, +L8A8_UINT , 16, 1, 1, 1, , , , ui8, ui8, , , linear, +L8A8_SINT , 16, 1, 1, 1, , , , si8, si8, , , linear, +R8_UNORM , 8, 1, 1, 1, un8, , , , , , , linear, +R8_SNORM , 8, 1, 1, 1, sn8, , , , , , , linear, +R8_SINT , 8, 1, 1, 1, si8, , , , , , , linear, +R8_UINT , 8, 1, 1, 1, ui8, , , , , , , linear, +A8_UNORM , 8, 1, 1, 1, , , , un8, , , , alpha, +I8_UNORM , 8, 1, 1, 1, , , , , , un8, , linear, +L8_UNORM , 8, 1, 1, 1, , , , , un8, , , linear, +P4A4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, +A4P4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, +R8_SSCALED , 8, 1, 1, 1, ss8, , , , , , , linear, +R8_USCALED , 8, 1, 1, 1, us8, , , , , , , linear, +P8_UNORM_PALETTE0 , 8, 1, 1, 1, , , , , , , un8, linear, +L8_UNORM_SRGB , 8, 1, 1, 1, , , , , un8, , , linear, +P8_UNORM_PALETTE1 , 8, 1, 1, 1, , , , , , , un8, linear, +P4A4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, +A4P4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, +Y8_UNORM , 0, 0, 0, 0, , , , , , , , yuv, +L8_UINT , 8, 1, 1, 1, , , , , ui8, , , linear, +L8_SINT , 8, 1, 1, 1, , , , , si8, , , linear, +I8_UINT , 8, 1, 1, 1, , , , , , ui8, , linear, +I8_SINT , 8, 1, 1, 1, , , , , , si8, , linear, +DXT1_RGB_SRGB , 64, 4, 4, 1, un4, un4, un4, , , , , srgb, dxt1 +R1_UNORM , 1, 1, 1, 1, un1, , , , , , , linear, +YCRCB_NORMAL , 0, 0, 0, 0, , , , , , , , yuv, +YCRCB_SWAPUVY , 0, 0, 0, 0, , , , , , , , yuv, +P2_UNORM_PALETTE0 , 2, 1, 1, 1, , , , , , , un2, linear, +P2_UNORM_PALETTE1 , 2, 1, 1, 1, , , , , , , un2, linear, +BC1_UNORM , 64, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt1 +BC2_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt3 +BC3_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt5 +BC4_UNORM , 64, 4, 4, 1, un8, , , , , , , linear, rgtc1 +BC5_UNORM , 128, 4, 4, 1, un8, un8, , , , , , linear, rgtc2 +BC1_UNORM_SRGB , 64, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt1 +BC2_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt3 +BC3_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt5 +MONO8 , 1, 1, 1, 1, , , , , , , , , +YCRCB_SWAPUV , 0, 0, 0, 0, , , , , , , , yuv, +YCRCB_SWAPY , 0, 0, 0, 0, , , , , , , , yuv, +DXT1_RGB , 64, 4, 4, 1, un4, un4, un4, , , , , linear, dxt1 +FXT1 , 128, 8, 4, 1, un4, un4, un4, , , , , linear, fxt1 +R8G8B8_UNORM , 24, 1, 1, 1, un8, un8, un8, , , , , linear, +R8G8B8_SNORM , 24, 1, 1, 1, sn8, sn8, sn8, , , , , linear, +R8G8B8_SSCALED , 24, 1, 1, 1, ss8, ss8, ss8, , , , , linear, +R8G8B8_USCALED , 24, 1, 1, 1, us8, us8, us8, , , , , linear, +R64G64B64A64_FLOAT , 256, 1, 1, 1, sf64, sf64, sf64, sf64, , , , linear, +R64G64B64_FLOAT , 196, 1, 1, 1, sf64, sf64, sf64, , , , , linear, +BC4_SNORM , 64, 4, 4, 1, sn8, , , , , , , linear, rgtc1 +BC5_SNORM , 128, 4, 4, 1, sn8, sn8, , , , , , linear, rgtc2 +R16G16B16_FLOAT , 48, 1, 1, 1, sf16, sf16, sf16, , , , , linear, +R16G16B16_UNORM , 48, 1, 1, 1, un16, un16, un16, , , , , linear, +R16G16B16_SNORM , 48, 1, 1, 1, sn16, sn16, sn16, , , , , linear, +R16G16B16_SSCALED , 48, 1, 1, 1, ss16, ss16, ss16, , , , , linear, +R16G16B16_USCALED , 48, 1, 1, 1, us16, us16, us16, , , , , linear, +BC6H_SF16 , 128, 4, 4, 1, sf16, sf16, sf16, , , , , linear, bptc +BC7_UNORM , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, bptc +BC7_UNORM_SRGB , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, bptc +BC6H_UF16 , 128, 4, 4, 1, uf16, uf16, uf16, , , , , linear, bptc +PLANAR_420_8 , 0, 0, 0, 0, , , , , , , , yuv, +R8G8B8_UNORM_SRGB , 24, 1, 1, 1, un8, un8, un8, , , , , srgb, +ETC1_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc1 +ETC2_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc2 +EAC_R11 , 64, 4, 4, 1, un11, , , , , , , linear, etc2 +EAC_RG11 , 128, 4, 4, 1, un11, un11, , , , , , linear, etc2 +EAC_SIGNED_R11 , 64, 4, 4, 1, sn11, , , , , , , linear, etc2 +EAC_SIGNED_RG11 , 128, 4, 4, 1, sn11, sn11, , , , , , linear, etc2 +ETC2_SRGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , srgb, etc2 +R16G16B16_UINT , 48, 1, 1, 1, ui16, ui16, ui16, , , , , linear, +R16G16B16_SINT , 48, 1, 1, 1, si16, si16, si16, , , , , linear, +R32_SFIXED , 32, 1, 1, 1, sx16, , , , , , , linear, +R10G10B10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, +R10G10B10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, +R10G10B10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, +R10G10B10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, +B10G10R10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, +B10G10R10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, +B10G10R10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, +B10G10R10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, +B10G10R10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, +R64G64B64A64_PASSTHRU , 256, 1, 1, 1, r64, r64, r64, r64, , , , , +R64G64B64_PASSTHRU , 192, 1, 1, 1, r64, r64, r64, , , , , , +ETC2_RGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , linear, etc2 +ETC2_SRGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , srgb, etc2 +ETC2_EAC_RGBA8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, etc2 +ETC2_EAC_SRGB8_A8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, etc2 +R8G8B8_UINT , 24, 1, 1, 1, ui8, ui8, ui8, , , , , linear, +R8G8B8_SINT , 24, 1, 1, 1, si8, si8, si8, , , , , linear, +RAW , 0, 0, 0, 0, , , , , , , , , diff --git a/src/intel/isl/isl_format_layout_gen.bash b/src/intel/isl/isl_format_layout_gen.bash new file mode 100755 index 00000000000..db883827376 --- /dev/null +++ b/src/intel/isl/isl_format_layout_gen.bash @@ -0,0 +1,128 @@ +#!/usr/bin/env bash +# +# Copyright 2015 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +set -eu +set -o pipefail + +cat <<'EOF' +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl.h" + +const struct isl_format_layout +isl_format_layouts[] = { +EOF + +sed -r ' +# Delete comment lines and empty lines +/^[[:space:]]*#/d +/^[[:space:]]*$/d + +# Delete spaces +s/[[:space:]]//g + +# Translate formats +s/^([A-Za-z0-9_]+),*/ISL_FORMAT_\1,/ + +# Translate data type of channels +s/\/ISL_COLORSPACE_\1/ +s/\// + +# Translate texture compression +s/\<(dxt|fxt|rgtc|bptc|etc)([0-9]*)\>/ISL_TXC_\1\2/ +' | +tr 'a-z' 'A-Z' | # Convert to uppersace +while IFS=, read -r format bpb bw bh bd \ + red green blue alpha \ + luminance intensity palette \ + colorspace txc +do + : ${colorspace:=ISL_COLORSPACE_NONE} + : ${txc:=ISL_TXC_NONE} + + cat <samples >= 1); + + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; +} + +void +gen4_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + assert(info->samples == 1); + assert(msaa_layout == ISL_MSAA_LAYOUT_NONE); + assert(!isl_tiling_is_std_y(tiling)); + + /* Note that neither the surface's horizontal nor vertical image alignment + * is programmable on gen4 nor gen5. + * + * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4 + * Alignment Unit Size: + * + * Note that the compressed formats are padded to a full compression + * cell. + * + * +------------------------+--------+--------+ + * | format | halign | valign | + * +------------------------+--------+--------+ + * | YUV 4:2:2 formats | 4 | 2 | + * | uncompressed formats | 4 | 2 | + * +------------------------+--------+--------+ + */ + + if (isl_format_is_compressed(info->format)) { + *image_align_el = isl_extent3d(1, 1, 1); + return; + } + + *image_align_el = isl_extent3d(4, 2, 1); +} diff --git a/src/intel/isl/isl_gen4.h b/src/intel/isl/isl_gen4.h new file mode 100644 index 00000000000..06cd70b9206 --- /dev/null +++ b/src/intel/isl/isl_gen4.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include "isl_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +gen4_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +gen4_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c new file mode 100644 index 00000000000..24c393925ed --- /dev/null +++ b/src/intel/isl/isl_gen6.c @@ -0,0 +1,160 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen6.h" +#include "isl_priv.h" + +bool +gen6_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(ISL_DEV_GEN(dev) == 6); + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return false; + } + + /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface + * Format: + * + * If Number of Multisamples is set to a value other than + * MULTISAMPLECOUNT_1, this field cannot be set to the following + * formats: + * + * - any format with greater than 64 bits per element + * - any compressed texture format (BC*) + * - any YCRCB* format + */ + if (fmtl->bs > 8) + return false; + if (isl_format_is_compressed(info->format)) + return false; + if (isl_format_is_yuv(info->format)) + return false; + + /* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of + * Multisamples: + * + * If this field is any value other than MULTISAMPLECOUNT_1 the + * following restrictions apply: + * + * - the Surface Type must be SURFTYPE_2D + * - [...] + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (tiling == ISL_TILING_LINEAR) + return false; + if (info->levels > 1) + return false; + + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; +} + +void +gen6_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* Note that the surface's horizontal image alignment is not programmable + * on Sandybridge. + * + * From the Sandybridge PRM (2011-05), Volume 1, Part 1, Section 7.18.3.4 + * Alignment Unit Size: + * + * Note that the compressed formats are padded to a full compression cell. + * + * +------------------------+--------+--------+ + * | format | halign | valign | + * +------------------------+--------+--------+ + * | YUV 4:2:2 formats | 4 | * | + * | uncompressed formats | 4 | * | + * +------------------------+--------+--------+ + * + * * For these formats, the vertical alignment factor “j” is determined + * as follows: + * - j = 4 for any depth buffer + * - j = 2 for separate stencil buffer + * - j = 4 for any render target surface is multisampled (4x) + * - j = 2 for all other render target surface + * + * From the Sandrybridge PRM (2011-05), Volume 4, Part 1, Section 2.11.2 + * SURFACE_STATE, Surface Vertical Alignment: + * + * - This field must be set to VALIGN_2 if the Surface Format is 96 bits + * per element (BPE). + * + * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL + * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY + * (0x190) + */ + + if (isl_format_is_compressed(info->format)) { + *image_align_el = isl_extent3d(1, 1, 1); + return; + } + + if (isl_format_is_yuv(info->format)) { + *image_align_el = isl_extent3d(4, 2, 1); + return; + } + + if (info->samples > 1) { + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_depth_or_stencil(info->usage) && + !ISL_DEV_USE_SEPARATE_STENCIL(dev)) { + /* interleaved depthstencil buffer */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_depth(info->usage)) { + /* separate depth buffer */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_stencil(info->usage)) { + /* separate stencil buffer */ + *image_align_el = isl_extent3d(4, 2, 1); + return; + } + + *image_align_el = isl_extent3d(4, 2, 1); +} diff --git a/src/intel/isl/isl_gen6.h b/src/intel/isl/isl_gen6.h new file mode 100644 index 00000000000..0779c674940 --- /dev/null +++ b/src/intel/isl/isl_gen6.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include "isl_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +gen6_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +gen6_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c new file mode 100644 index 00000000000..7064e852e65 --- /dev/null +++ b/src/intel/isl/isl_gen7.c @@ -0,0 +1,395 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen7.h" +#include "isl_priv.h" + +bool +gen7_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + bool require_array = false; + bool require_interleaved = false; + + assert(ISL_DEV_GEN(dev) == 7); + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; + } + + /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface + * Format: + * + * If Number of Multisamples is set to a value other than + * MULTISAMPLECOUNT_1, this field cannot be set to the following + * formats: any format with greater than 64 bits per element, any + * compressed texture format (BC*), and any YCRCB* format. + */ + if (fmtl->bs > 8) + return false; + if (isl_format_is_compressed(info->format)) + return false; + if (isl_format_is_yuv(info->format)) + return false; + + /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of + * Multisamples: + * + * - If this field is any value other than MULTISAMPLECOUNT_1, the + * Surface Type must be SURFTYPE_2D. + * + * - If this field is any value other than MULTISAMPLECOUNT_1, Surface + * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + if (info->levels > 1) + return false; + + /* The Ivyrbridge PRM insists twice that signed integer formats cannot be + * multisampled. + * + * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of + * Multisamples: + * + * - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when + * all RT channels are not written. + * + * And errata from the Ivybridge PRM, Volume 4 Part 1 p77, + * RENDER_SURFACE_STATE, MCS Enable: + * + * This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs + * when all RT channels are not written. + * + * Note that the above SINT restrictions apply only to *MSRTs* (that is, + * *multisampled* render targets). The restrictions seem to permit an MCS + * if the render target is singlesampled. + */ + if (isl_format_has_sint_channel(info->format)) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (tiling == ISL_TILING_LINEAR) + return false; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * +---------------------+----------------------------------------------------------------+ + * | MSFMT_MSS | Multsampled surface was/is rendered as a render target | + * | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer | + * +---------------------+----------------------------------------------------------------+ + * + * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and + * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED. + */ + if (isl_surf_usage_is_depth_or_stencil(info->usage)) + require_interleaved = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width + * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this + * field must be set to MSFMT_MSS. + */ + if (info->samples == 8 && info->width == 8192) + require_array = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, + * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number + * of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is + * > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL. + */ + if ((info->samples == 8 && info->height > 4194304u) || + (info->samples == 4 && info->height > 8388608u)) + require_interleaved = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is + * one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or + * R24_UNORM_X8_TYPELESS. + */ + if (info->format == ISL_FORMAT_I24X8_UNORM || + info->format == ISL_FORMAT_L24X8_UNORM || + info->format == ISL_FORMAT_A24X8_UNORM || + info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) + require_interleaved = true; + + if (require_array && require_interleaved) + return false; + + if (require_interleaved) { + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; + } + + /* Default to the array layout because it permits multisample + * compression. + */ + *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; + return true; +} + +static bool +gen7_format_needs_valign2(const struct isl_device *dev, + enum isl_format format) +{ + /* This workaround applies only to gen7 */ + if (ISL_DEV_GEN(dev) > 7) + return false; + + /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, + * RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL + * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY + * (0x190) + * + * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT. + */ + return isl_format_is_yuv(format) || + format == ISL_FORMAT_R32G32B32_FLOAT; +} + +/** + * @brief Filter out tiling flags that are incompatible with the surface. + * + * The resultant outgoing @a flags is a subset of the incoming @a flags. The + * outgoing flags may be empty (0x0) if the incoming flags were too + * restrictive. + * + * For example, if the surface will be used for a display + * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling + * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT. + */ +void +gen7_filter_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + isl_tiling_flags_t *flags) +{ + /* IVB+ requires separate stencil */ + assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); + + /* Clear flags unsupported on this hardware */ + if (ISL_DEV_GEN(dev) < 9) { + *flags &= ~ISL_TILING_Yf_BIT; + *flags &= ~ISL_TILING_Ys_BIT; + } + + /* And... clear the Yf and Ys bits anyway because Anvil doesn't support + * them yet. + */ + *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */ + *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */ + + if (isl_surf_usage_is_depth(info->usage)) { + /* Depth requires Y. */ + *flags &= ISL_TILING_ANY_Y_MASK; + } + + /* Separate stencil requires W tiling, and W tiling requires separate + * stencil. + */ + if (isl_surf_usage_is_stencil(info->usage)) { + *flags &= ISL_TILING_W_BIT; + } else { + *flags &= ~ISL_TILING_W_BIT; + } + + if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | + ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | + ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { + assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); + isl_finishme("%s:%s: handle rotated display surfaces", + __FILE__, __func__); + } + + if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT | + ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) { + assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); + isl_finishme("%s:%s: handle flipped display surfaces", + __FILE__, __func__); + } + + if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) { + /* Before Skylake, the display engine does not accept Y */ + /* FINISHME[SKL]: Y tiling for display surfaces */ + *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT); + } + + if (info->samples > 1) { + /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled + * Surface: + * + * For multisample render targets, this field must be 1 (true). MSRTs + * can only be tiled. + * + * Multisample surfaces never require X tiling, and Y tiling generally + * performs better than X. So choose Y. (Unless it's stencil, then it + * must be W). + */ + *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT); + } + + /* workaround */ + if (ISL_DEV_GEN(dev) == 7 && + gen7_format_needs_valign2(dev, info->format) && + (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + info->samples == 1) { + /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1, + * SURFACE_STATE Surface Vertical Alignment: + * + * This field must be set to VALIGN_4 for all tiled Y Render Target + * surfaces. + */ + *flags &= ~ISL_TILING_Y0_BIT; + } +} + +/** + * Choose horizontal subimage alignment, in units of surface elements. + */ +static uint32_t +gen7_choose_halign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + if (isl_format_is_compressed(info->format)) + return 1; + + /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, + * RENDER_SURFACE_STATE Surface Hoizontal Alignment: + * + * - This field is intended to be set to HALIGN_8 only if the surface + * was rendered as a depth buffer with Z16 format or a stencil buffer, + * since these surfaces support only alignment of 8. Use of HALIGN_8 + * for other surfaces is supported, but uses more memory. + */ + if (isl_surf_info_is_z16(info) || + isl_surf_usage_is_stencil(info->usage)) + return 8; + + return 4; +} + +/** + * Choose vertical subimage alignment, in units of surface elements. + */ +static uint32_t +gen7_choose_valign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling) +{ + bool require_valign2 = false; + bool require_valign4 = false; + + if (isl_format_is_compressed(info->format)) + return 1; + + if (gen7_format_needs_valign2(dev, info->format)) + require_valign2 = true; + + /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1: + * RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - This field is intended to be set to VALIGN_4 if the surface was + * rendered as a depth buffer, for a multisampled (4x) render target, + * or for a multisampled (8x) render target, since these surfaces + * support only alignment of 4. Use of VALIGN_4 for other surfaces is + * supported, but uses more memory. This field must be set to + * VALIGN_4 for all tiled Y Render Target surfaces. + * + */ + if (isl_surf_usage_is_depth(info->usage) || + info->samples > 1 || + tiling == ISL_TILING_Y0) { + require_valign4 = true; + } + + if (isl_surf_usage_is_stencil(info->usage)) { + /* The Ivybridge PRM states that the stencil buffer's vertical alignment + * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment + * Unit Size]. However, valign=8 is outside the set of valid values of + * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2 + * (0x0) and VALIGN_4 (0x1). + * + * The PRM is generally confused about the width, height, and alignment + * of the stencil buffer; and this confusion appears elsewhere. For + * example, the following PRM text effectively converts the stencil + * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM, + * Volume 1, Part 1, Section + * 6.18.4.2 Base Address and LOD Calculation]: + * + * For separate stencil buffer, the width must be mutiplied by 2 and + * height divided by 2 as follows: + * + * w_L = 2*i*ceil(W_L/i) + * h_L = 1/2*j*ceil(H_L/j) + * + * The root of the confusion is that, in W tiling, each pair of rows is + * interleaved into one. + * + * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API + * is more polished. + */ + require_valign4 = true; + } + + assert(!require_valign2 || !require_valign4); + + if (require_valign4) + return 4; + + /* Prefer VALIGN_2 because it conserves memory. */ + return 2; +} + +void +gen7_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* IVB+ does not support combined depthstencil. */ + assert(!isl_surf_usage_is_depth_and_stencil(info->usage)); + + *image_align_el = (struct isl_extent3d) { + .w = gen7_choose_halign_el(dev, info), + .h = gen7_choose_valign_el(dev, info, tiling), + .d = 1, + }; +} diff --git a/src/intel/isl/isl_gen7.h b/src/intel/isl/isl_gen7.h new file mode 100644 index 00000000000..2a95b68a9bd --- /dev/null +++ b/src/intel/isl/isl_gen7.h @@ -0,0 +1,52 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include "isl_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void +gen7_filter_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + isl_tiling_flags_t *flags); + +bool +gen7_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +gen7_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c new file mode 100644 index 00000000000..a46427aacc8 --- /dev/null +++ b/src/intel/isl/isl_gen8.c @@ -0,0 +1,229 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen8.h" +#include "isl_priv.h" + +bool +gen8_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + bool require_array = false; + bool require_interleaved = false; + + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; + } + + /* From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Tile Mode: + * + * - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field + * must be YMAJOR. + * + * As usual, though, stencil is special. + */ + if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage)) + return false; + + /* From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Multisampled Surface Storage Format: + * + * All multisampled render target surfaces must have this field set to + * MSFMT_MSS + */ + if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + require_array = true; + + /* From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Number of Multisamples: + * + * - If this field is any value other than MULTISAMPLECOUNT_1, the + * Surface Type must be SURFTYPE_2D This field must be set to + * MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface + * or Render Target surface. + * + * - If this field is any value other than MULTISAMPLECOUNT_1, Surface + * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero. + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + if (info->levels > 1) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (isl_format_is_compressed(info->format)) + return false; + if (isl_format_is_yuv(info->format)) + return false; + + if (isl_surf_usage_is_depth_or_stencil(info->usage)) + require_interleaved = true; + + if (require_array && require_interleaved) + return false; + + if (require_interleaved) { + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; + } + + *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; + return true; +} + +/** + * Choose horizontal subimage alignment, in units of surface elements. + */ +static uint32_t +gen8_choose_halign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + if (isl_format_is_compressed(info->format)) + return 1; + + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * - This field is intended to be set to HALIGN_8 only if the surface + * was rendered as a depth buffer with Z16 format or a stencil buffer. + * In this case it must be set to HALIGN_8 since these surfaces + * support only alignment of 8. [...] + */ + if (isl_surf_info_is_z16(info)) + return 8; + if (isl_surf_usage_is_stencil(info->usage)) + return 8; + + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * [...] For Z32 formats it must be set to HALIGN_4. + */ + if (isl_surf_usage_is_depth(info->usage)) + return 4; + + if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, + * HALIGN 16 must be used. + * + * This case handles color surfaces that may own an auxiliary MCS, CCS_D, + * or CCS_E. Depth buffers, including those that own an auxiliary HiZ + * surface, are handled above and do not require HALIGN_16. + */ + assert(!isl_surf_usage_is_depth(info->usage)); + return 16; + } + + /* XXX(chadv): I believe the hardware requires each image to be + * cache-aligned. If that's true, then defaulting to halign=4 is wrong for + * many formats. Depending on the format's block size, we may need to + * increase halign to 8. + */ + return 4; +} + +/** + * Choose vertical subimage alignment, in units of surface elements. + */ +static uint32_t +gen8_choose_valign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + /* From the Broadwell PRM > Volume 2d: Command Reference: Structures + * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325): + * + * - For Sampling Engine and Render Target Surfaces: This field + * specifies the vertical alignment requirement in elements for the + * surface. [...] An element is defined as a pixel in uncompresed + * surface formats, and as a compression block in compressed surface + * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an + * element is a sample. + * + * - This field is intended to be set to VALIGN_4 if the surface was + * rendered as a depth buffer, for a multisampled (4x) render target, + * or for a multisampled (8x) render target, since these surfaces + * support only alignment of 4. Use of VALIGN_4 for other surfaces is + * supported, but increases memory usage. + * + * - This field is intended to be set to VALIGN_8 only if the surface + * was rendered as a stencil buffer, since stencil buffer surfaces + * support only alignment of 8. If set to VALIGN_8, Surface Format + * must be R8_UINT. + */ + + if (isl_format_is_compressed(info->format)) + return 1; + + if (isl_surf_usage_is_stencil(info->usage)) + return 8; + + return 4; +} + +void +gen8_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + assert(!isl_tiling_is_std_y(tiling)); + + /* The below text from the Broadwell PRM provides some insight into the + * hardware's requirements for LOD alignment. From the Broadwell PRM >> + * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: + * + * These [2D surfaces] must adhere to the following memory organization + * rules: + * + * - For non-compressed texture formats, each mipmap must start on an + * even row within the monolithic rectangular area. For + * 1-texel-high mipmaps, this may require a row of padding below + * the previous mipmap. This restriction does not apply to any + * compressed texture formats; each subsequent (lower-res) + * compressed mipmap is positioned directly below the previous + * mipmap. + * + * - Vertical alignment restrictions vary with memory tiling type: + * 1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled + * mipmaps are not required to start at the left edge of a tile + * row.) + */ + + *image_align_el = (struct isl_extent3d) { + .w = gen8_choose_halign_el(dev, info), + .h = gen8_choose_valign_el(dev, info), + .d = 1, + }; +} diff --git a/src/intel/isl/isl_gen8.h b/src/intel/isl/isl_gen8.h new file mode 100644 index 00000000000..2017ea8ddc1 --- /dev/null +++ b/src/intel/isl/isl_gen8.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include "isl_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +gen8_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +gen8_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c new file mode 100644 index 00000000000..aa290aa1c35 --- /dev/null +++ b/src/intel/isl/isl_gen9.c @@ -0,0 +1,185 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen8.h" +#include "isl_gen9.h" +#include "isl_priv.h" + +/** + * Calculate the surface's subimage alignment, in units of surface samples, + * for the standard tiling formats Yf and Ys. + */ +static void +gen9_calc_std_image_alignment_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *align_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(isl_tiling_is_std_y(tiling)); + + const uint32_t bs = fmtl->bs; + const uint32_t is_Ys = tiling == ISL_TILING_Ys; + + switch (info->dim) { + case ISL_SURF_DIM_1D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (12 - (ffs(bs) - 1) + (4 * is_Ys)), + .h = 1, + .d = 1, + }; + return; + case ISL_SURF_DIM_2D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > + * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment + * Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (6 - ((ffs(bs) - 1) / 2) + (4 * is_Ys)), + .h = 1 << (6 - ((ffs(bs) - 0) / 2) + (4 * is_Ys)), + .d = 1, + }; + + if (is_Ys) { + /* FINISHME(chadv): I don't trust this code. Untested. */ + isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__); + + switch (msaa_layout) { + case ISL_MSAA_LAYOUT_NONE: + case ISL_MSAA_LAYOUT_INTERLEAVED: + break; + case ISL_MSAA_LAYOUT_ARRAY: + align_sa->w >>= (ffs(info->samples) - 0) / 2; + align_sa->h >>= (ffs(info->samples) - 1) / 2; + break; + } + } + return; + + case ISL_SURF_DIM_3D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (4 - ((ffs(bs) + 1) / 3) + (4 * is_Ys)), + .h = 1 << (4 - ((ffs(bs) - 1) / 3) + (2 * is_Ys)), + .d = 1 << (4 - ((ffs(bs) - 0) / 3) + (2 * is_Ys)), + }; + return; + } + + unreachable("bad isl_surface_type"); +} + +void +gen9_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* This BSpec text provides some insight into the hardware's alignment + * requirements [Skylake BSpec > Memory Views > Common Surface Formats > + * Surface Layout and Tiling > 2D Surfaces]: + * + * An LOD must be aligned to a cache-line except for some special cases + * related to Planar YUV surfaces. In general, the cache-alignment + * restriction implies there is a minimum height for an LOD of 4 texels. + * So, LODs which are smaller than 4 high are padded. + * + * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - For Sampling Engine and Render Target Surfaces: This field + * specifies the vertical alignment requirement in elements for the + * surface. [...] An element is defined as a pixel in uncompresed + * surface formats, and as a compression block in compressed surface + * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an + * element is a sample. + * + * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled + * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled). + * This field is ignored for 1D surfaces and also when Tiled Resource + * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled). + * + * See the appropriate Alignment table in the "Surface Layout and + * Tiling" section under Common Surface Formats for the table of + * alignment values for Tiled Resrouces. + * + * - For uncompressed surfaces, the units of "j" are rows of pixels on + * the physical surface. For compressed texture formats, the units of + * "j" are in compression blocks, thus each increment in "j" is equal + * to h pixels, where h is the height of the compression block in + * pixels. + * + * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16 + * + * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal + * Alignment: + * + * - For uncompressed surfaces, the units of "i" are pixels on the + * physical surface. For compressed texture formats, the units of "i" + * are in compression blocks, thus each increment in "i" is equal to + * w pixels, where w is the width of the compression block in pixels. + * + * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16 + */ + + if (isl_tiling_is_std_y(tiling)) { + struct isl_extent3d image_align_sa; + gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, + &image_align_sa); + + *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa); + return; + } + + if (info->dim == ISL_SURF_DIM_1D) { + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *image_align_el = isl_extent3d(64, 1, 1); + return; + } + + if (isl_format_is_compressed(info->format)) { + /* On Gen9, the meaning of RENDER_SURFACE_STATE's + * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for + * compressed formats. They now indicate a multiple of the compression + * block. For example, if the compression mode is ETC2 then HALIGN_4 + * indicates a horizontal alignment of 16 pixels. + * + * To avoid wasting memory, choose the smallest alignment possible: + * HALIGN_4 and VALIGN_4. + */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout, + image_align_el); +} diff --git a/src/intel/isl/isl_gen9.h b/src/intel/isl/isl_gen9.h new file mode 100644 index 00000000000..64ed0aa44ef --- /dev/null +++ b/src/intel/isl/isl_gen9.h @@ -0,0 +1,41 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include "isl_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void +gen9_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif diff --git a/src/intel/isl/isl_image.c b/src/intel/isl/isl_image.c new file mode 100644 index 00000000000..773160432b9 --- /dev/null +++ b/src/intel/isl/isl_image.c @@ -0,0 +1,188 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl.h" +#include "brw_compiler.h" + +bool +isl_is_storage_image_format(enum isl_format format) +{ + /* XXX: Maybe we should put this in the CSV? */ + + switch (format) { + case ISL_FORMAT_R32G32B32A32_UINT: + case ISL_FORMAT_R32G32B32A32_SINT: + case ISL_FORMAT_R32G32B32A32_FLOAT: + case ISL_FORMAT_R32_UINT: + case ISL_FORMAT_R32_SINT: + case ISL_FORMAT_R32_FLOAT: + case ISL_FORMAT_R16G16B16A16_UINT: + case ISL_FORMAT_R16G16B16A16_SINT: + case ISL_FORMAT_R16G16B16A16_FLOAT: + case ISL_FORMAT_R32G32_UINT: + case ISL_FORMAT_R32G32_SINT: + case ISL_FORMAT_R32G32_FLOAT: + case ISL_FORMAT_R8G8B8A8_UINT: + case ISL_FORMAT_R8G8B8A8_SINT: + case ISL_FORMAT_R16G16_UINT: + case ISL_FORMAT_R16G16_SINT: + case ISL_FORMAT_R16G16_FLOAT: + case ISL_FORMAT_R8G8_UINT: + case ISL_FORMAT_R8G8_SINT: + case ISL_FORMAT_R16_UINT: + case ISL_FORMAT_R16_FLOAT: + case ISL_FORMAT_R16_SINT: + case ISL_FORMAT_R8_UINT: + case ISL_FORMAT_R8_SINT: + case ISL_FORMAT_R10G10B10A2_UINT: + case ISL_FORMAT_R10G10B10A2_UNORM: + case ISL_FORMAT_R11G11B10_FLOAT: + case ISL_FORMAT_R16G16B16A16_UNORM: + case ISL_FORMAT_R16G16B16A16_SNORM: + case ISL_FORMAT_R8G8B8A8_UNORM: + case ISL_FORMAT_R8G8B8A8_SNORM: + case ISL_FORMAT_R16G16_UNORM: + case ISL_FORMAT_R16G16_SNORM: + case ISL_FORMAT_R8G8_UNORM: + case ISL_FORMAT_R8G8_SNORM: + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R16_SNORM: + case ISL_FORMAT_R8_UNORM: + case ISL_FORMAT_R8_SNORM: + return true; + default: + return false; + } +} + +enum isl_format +isl_lower_storage_image_format(const struct isl_device *dev, + enum isl_format format) +{ + switch (format) { + /* These are never lowered. Up to BDW we'll have to fall back to untyped + * surface access for 128bpp formats. + */ + case ISL_FORMAT_R32G32B32A32_UINT: + case ISL_FORMAT_R32G32B32A32_SINT: + case ISL_FORMAT_R32G32B32A32_FLOAT: + case ISL_FORMAT_R32_UINT: + case ISL_FORMAT_R32_SINT: + case ISL_FORMAT_R32_FLOAT: + return format; + + /* From HSW to BDW the only 64bpp format supported for typed access is + * RGBA_UINT16. IVB falls back to untyped. + */ + case ISL_FORMAT_R16G16B16A16_UINT: + case ISL_FORMAT_R16G16B16A16_SINT: + case ISL_FORMAT_R16G16B16A16_FLOAT: + case ISL_FORMAT_R32G32_UINT: + case ISL_FORMAT_R32G32_SINT: + case ISL_FORMAT_R32G32_FLOAT: + return (ISL_DEV_GEN(dev) >= 9 ? format : + ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R16G16B16A16_UINT : + ISL_FORMAT_R32G32_UINT); + + /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component + * are supported. IVB doesn't support formats with more than one component + * for typed access. For 8 and 16 bpp formats IVB relies on the + * undocumented behavior that typed reads from R_UINT8 and R_UINT16 + * surfaces actually do a 32-bit misaligned read. The alternative would be + * to use two surface state entries with different formats for each image, + * one for reading (using R_UINT32) and another one for writing (using + * R_UINT8 or R_UINT16), but that would complicate the shaders we generate + * even more. + */ + case ISL_FORMAT_R8G8B8A8_UINT: + case ISL_FORMAT_R8G8B8A8_SINT: + return (ISL_DEV_GEN(dev) >= 9 ? format : + ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R16G16_UINT: + case ISL_FORMAT_R16G16_SINT: + case ISL_FORMAT_R16G16_FLOAT: + return (ISL_DEV_GEN(dev) >= 9 ? format : + ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R8G8_UINT: + case ISL_FORMAT_R8G8_SINT: + return (ISL_DEV_GEN(dev) >= 9 ? format : + ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R16_UINT: + case ISL_FORMAT_R16_FLOAT: + case ISL_FORMAT_R16_SINT: + return (ISL_DEV_GEN(dev) >= 9 ? format : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R8_UINT: + case ISL_FORMAT_R8_SINT: + return (ISL_DEV_GEN(dev) >= 9 ? format : ISL_FORMAT_R8_UINT); + + /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported + * by the hardware. + */ + case ISL_FORMAT_R10G10B10A2_UINT: + case ISL_FORMAT_R10G10B10A2_UNORM: + case ISL_FORMAT_R11G11B10_FLOAT: + return ISL_FORMAT_R32_UINT; + + /* No normalized fixed-point formats are supported by the hardware. */ + case ISL_FORMAT_R16G16B16A16_UNORM: + case ISL_FORMAT_R16G16B16A16_SNORM: + return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R16G16B16A16_UINT : + ISL_FORMAT_R32G32_UINT); + + case ISL_FORMAT_R8G8B8A8_UNORM: + case ISL_FORMAT_R8G8B8A8_SNORM: + return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R16G16_UNORM: + case ISL_FORMAT_R16G16_SNORM: + return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R8G8_UNORM: + case ISL_FORMAT_R8G8_SNORM: + return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? + ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R16_SNORM: + return ISL_FORMAT_R16_UINT; + + case ISL_FORMAT_R8_UNORM: + case ISL_FORMAT_R8_SNORM: + return ISL_FORMAT_R8_UINT; + + default: + assert(!"Unknown image format"); + return ISL_FORMAT_UNSUPPORTED; + } +} diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h new file mode 100644 index 00000000000..b399e0f8116 --- /dev/null +++ b/src/intel/isl/isl_priv.h @@ -0,0 +1,141 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#include + +#include "brw_device_info.h" +#include "mesa/main/imports.h" +#include "util/macros.h" + +#include "isl.h" + +#define isl_finishme(format, ...) \ + __isl_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__) + +void PRINTFLIKE(3, 4) UNUSED +__isl_finishme(const char *file, int line, const char *fmt, ...); + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +static inline uint32_t +ffs(uint32_t n) { + return __builtin_ffs(n); +} + +static inline bool +isl_is_pow2(uintmax_t n) +{ + return !(n & (n - 1)); +} + +/** + * Alignment must be a power of 2. + */ +static inline bool +isl_is_aligned(uintmax_t n, uintmax_t a) +{ + assert(isl_is_pow2(a)); + return (n & (a - 1)) == 0; +} + +/** + * Alignment must be a power of 2. + */ +static inline uintmax_t +isl_align(uintmax_t n, uintmax_t a) +{ + assert(a != 0 && isl_is_pow2(a)); + return (n + a - 1) & ~(a - 1); +} + +static inline uintmax_t +isl_align_npot(uintmax_t n, uintmax_t a) +{ + assert(a > 0); + return ((n + a - 1) / a) * a; +} + +/** + * Alignment must be a power of 2. + */ +static inline uintmax_t +isl_align_div(uintmax_t n, uintmax_t a) +{ + return isl_align(n, a) / a; +} + +static inline uintmax_t +isl_align_div_npot(uintmax_t n, uintmax_t a) +{ + return isl_align_npot(n, a) / a; +} + +/** + * Log base 2, rounding towards zero. + */ +static inline uint32_t +isl_log2u(uint32_t n) +{ + assert(n != 0); + return 31 - __builtin_clz(n); +} + +static inline uint32_t +isl_minify(uint32_t n, uint32_t levels) +{ + if (unlikely(n == 0)) + return 0; + else + return MAX(n >> levels, 1); +} + +static inline struct isl_extent3d +isl_extent3d_sa_to_el(enum isl_format fmt, struct isl_extent3d extent_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + assert(extent_sa.w % fmtl->bw == 0); + assert(extent_sa.h % fmtl->bh == 0); + assert(extent_sa.d % fmtl->bd == 0); + + return (struct isl_extent3d) { + .w = extent_sa.w / fmtl->bw, + .h = extent_sa.h / fmtl->bh, + .d = extent_sa.d / fmtl->bd, + }; +} + +static inline struct isl_extent3d +isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return (struct isl_extent3d) { + .w = extent_el.w * fmtl->bw, + .h = extent_el.h * fmtl->bh, + .d = extent_el.d * fmtl->bd, + }; +} diff --git a/src/intel/isl/tests/.gitignore b/src/intel/isl/tests/.gitignore new file mode 100644 index 00000000000..ba70ecfbee4 --- /dev/null +++ b/src/intel/isl/tests/.gitignore @@ -0,0 +1 @@ +/isl_surf_get_image_offset_test diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c new file mode 100644 index 00000000000..cda8583daeb --- /dev/null +++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -0,0 +1,353 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "brw_device_info.h" +#include "isl.h" +#include "isl_priv.h" + +#define BDW_GT2_DEVID 0x161a + +// An asssert that works regardless of NDEBUG. +#define t_assert(cond) \ + do { \ + if (!(cond)) { \ + fprintf(stderr, "%s:%d: assertion failed\n", __FILE__, __LINE__); \ + abort(); \ + } \ + } while (0) + +static void +t_assert_extent4d(const struct isl_extent4d *e, uint32_t width, + uint32_t height, uint32_t depth, uint32_t array_len) +{ + t_assert(e->width == width); + t_assert(e->height == height); + t_assert(e->depth == depth); + t_assert(e->array_len == array_len); +} + +static void +t_assert_image_alignment_el(const struct isl_surf *surf, + uint32_t w, uint32_t h, uint32_t d) +{ + struct isl_extent3d align_el; + + align_el = isl_surf_get_image_alignment_el(surf); + t_assert(align_el.w == w); + t_assert(align_el.h == h); + t_assert(align_el.d == d); + +} + +static void +t_assert_image_alignment_sa(const struct isl_surf *surf, + uint32_t w, uint32_t h, uint32_t d) +{ + struct isl_extent3d align_sa; + + align_sa = isl_surf_get_image_alignment_sa(surf); + t_assert(align_sa.w == w); + t_assert(align_sa.h == h); + t_assert(align_sa.d == d); + +} + +static void +t_assert_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t expected_x_offset_el, + uint32_t expected_y_offset_el) +{ + uint32_t x, y; + isl_surf_get_image_offset_el(surf, level, logical_array_layer, + logical_z_offset_px, &x, &y); + + t_assert(x == expected_x_offset_el); + t_assert(y == expected_y_offset_el); +} + +static void +t_assert_intratile_offset_el(const struct isl_device *dev, + const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t expected_base_address_offset, + uint32_t expected_x_offset_el, + uint32_t expected_y_offset_el) +{ + uint32_t base_address_offset; + uint32_t x_offset_el, y_offset_el; + isl_surf_get_image_intratile_offset_el(dev, surf, + level, + logical_array_layer, + logical_z_offset_px, + &base_address_offset, + &x_offset_el, + &y_offset_el); + + t_assert(base_address_offset == expected_base_address_offset); + t_assert(x_offset_el == expected_x_offset_el); + t_assert(y_offset_el == expected_y_offset_el); +} + +static void +t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width, + uint32_t height, uint32_t depth, uint32_t array_len) +{ + t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len); +} + +static void +t_assert_gen4_3d_layer(const struct isl_surf *surf, + uint32_t level, + uint32_t aligned_width, + uint32_t aligned_height, + uint32_t depth, + uint32_t horiz_layers, + uint32_t vert_layers, + uint32_t *base_y) +{ + for (uint32_t z = 0; z < depth; ++z) { + t_assert_offset_el(surf, level, 0, z, + aligned_width * (z % horiz_layers), + *base_y + aligned_height * (z / horiz_layers)); + } + + *base_y += aligned_height * vert_layers; +} + +static void +test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void) +{ + bool ok; + + struct isl_device dev; + isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), + /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_2D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 512, + .height = 512, + .depth = 1, + .levels = 10, + .array_len = 1, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + t_assert_phys_level0_sa(&surf, 512, 512, 1, 1); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 772); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == + isl_surf_get_array_pitch_sa_rows(&surf)); + + /* Row pitch should be minimal possible */ + t_assert(surf.row_pitch == 2048); + + t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0 + t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512 + t_assert_offset_el(&surf, 2, 0, 0, 256, 512); // +256, +0 + t_assert_offset_el(&surf, 3, 0, 0, 256, 640); // +0, +128 + t_assert_offset_el(&surf, 4, 0, 0, 256, 704); // +0, +64 + t_assert_offset_el(&surf, 5, 0, 0, 256, 736); // +0, +32 + t_assert_offset_el(&surf, 6, 0, 0, 256, 752); // +0, +16 + t_assert_offset_el(&surf, 7, 0, 0, 256, 760); // +0, +8 + t_assert_offset_el(&surf, 8, 0, 0, 256, 764); // +0, +4 + t_assert_offset_el(&surf, 9, 0, 0, 256, 768); // +0, +4 + + t_assert_intratile_offset_el(&dev, &surf, 0, 0, 0, 0x0, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 1, 0, 0, 0x100000, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 2, 0, 0, 0x100400, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 3, 0, 0, 0x140400, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 4, 0, 0, 0x160400, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 5, 0, 0, 0x170400, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 6, 0, 0, 0x170400, 0, 16); + t_assert_intratile_offset_el(&dev, &surf, 7, 0, 0, 0x170400, 0, 24); + t_assert_intratile_offset_el(&dev, &surf, 8, 0, 0, 0x170400, 0, 28); + t_assert_intratile_offset_el(&dev, &surf, 9, 0, 0, 0x180400, 0, 0); +} + +static void +test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void) +{ + bool ok; + + struct isl_device dev; + isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), + /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_2D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 1024, + .height = 1024, + .depth = 1, + .levels = 11, + .array_len = 6, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + + t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 1540); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == + isl_surf_get_array_pitch_sa_rows(&surf)); + + /* Row pitch should be minimal possible */ + t_assert(surf.row_pitch == 4096); + + for (uint32_t a = 0; a < 6; ++a) { + uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf); + + t_assert_offset_el(&surf, 0, a, 0, 0, b + 0); // +0, +0 + t_assert_offset_el(&surf, 1, a, 0, 0, b + 1024); // +0, +1024 + t_assert_offset_el(&surf, 2, a, 0, 512, b + 1024); // +512, +0 + t_assert_offset_el(&surf, 3, a, 0, 512, b + 1280); // +0, +256 + t_assert_offset_el(&surf, 4, a, 0, 512, b + 1408); // +0, +128 + t_assert_offset_el(&surf, 5, a, 0, 512, b + 1472); // +0, +64 + t_assert_offset_el(&surf, 6, a, 0, 512, b + 1504); // +0, +32 + t_assert_offset_el(&surf, 7, a, 0, 512, b + 1520); // +0, +16 + t_assert_offset_el(&surf, 8, a, 0, 512, b + 1528); // +0, +8 + t_assert_offset_el(&surf, 9, a, 0, 512, b + 1532); // +0, +4 + t_assert_offset_el(&surf, 10, a, 0, 512, b + 1536); // +0, +4 + + } + + /* The layout below assumes a specific array pitch. It will need updating + * if isl's array pitch calculations ever change. + */ + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 1540); + + /* array layer 0 */ + t_assert_intratile_offset_el(&dev, &surf, 0, 0, 0, 0x0, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 1, 0, 0, 0x400000, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 2, 0, 0, 0x400800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 3, 0, 0, 0x500800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 4, 0, 0, 0x580800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 5, 0, 0, 0x5c0800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 6, 0, 0, 0x5e0800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 7, 0, 0, 0x5e0800, 0, 16); + t_assert_intratile_offset_el(&dev, &surf, 8, 0, 0, 0x5e0800, 0, 24); + t_assert_intratile_offset_el(&dev, &surf, 9, 0, 0, 0x5e0800, 0, 28); + t_assert_intratile_offset_el(&dev, &surf, 10, 0, 0, 0x600800, 0, 0); + + /* array layer 1 */ + t_assert_intratile_offset_el(&dev, &surf, 0, 1, 0, 0x600000, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 1, 1, 0, 0xa00000, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 2, 1, 0, 0xa00800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 3, 1, 0, 0xb00800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 4, 1, 0, 0xb80800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 5, 1, 0, 0xbc0800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 6, 1, 0, 0xbe0800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 7, 1, 0, 0xbe0800, 0, 20); + t_assert_intratile_offset_el(&dev, &surf, 8, 1, 0, 0xbe0800, 0, 28); + t_assert_intratile_offset_el(&dev, &surf, 9, 1, 0, 0xc00800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 10, 1, 0, 0xc00800, 0, 4); + + /* array layer 2 */ + t_assert_intratile_offset_el(&dev, &surf, 0, 2, 0, 0xc00000, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 1, 2, 0, 0x1000000, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 2, 2, 0, 0x1000800, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 3, 2, 0, 0x1100800, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 4, 2, 0, 0x1180800, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 5, 2, 0, 0x11c0800, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 6, 2, 0, 0x11e0800, 0, 8); + t_assert_intratile_offset_el(&dev, &surf, 7, 2, 0, 0x11e0800, 0, 24); + t_assert_intratile_offset_el(&dev, &surf, 8, 2, 0, 0x1200800, 0, 0); + t_assert_intratile_offset_el(&dev, &surf, 9, 2, 0, 0x1200800, 0, 4); + t_assert_intratile_offset_el(&dev, &surf, 10, 2, 0, 0x1200800, 0, 8); + + /* skip the remaining array layers */ +} + +static void +test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void) +{ + bool ok; + + struct isl_device dev; + isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), + /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_3D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 256, + .height = 256, + .depth = 256, + .levels = 9, + .array_len = 1, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 74916); + t_assert(isl_surf_get_array_pitch_sa_rows(&surf) == + isl_surf_get_array_pitch_el_rows(&surf)); + + uint32_t base_y = 0; + + t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y); + t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y); + t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y); + t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y); + t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y); +} + +int main(void) +{ + /* FINISHME: Add tests for npot sizes */ + /* FINISHME: Add tests for 1D surfaces */ + + test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(); + test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(); + test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(); +} diff --git a/src/isl/.gitignore b/src/isl/.gitignore deleted file mode 100644 index e9cfd67b94e..00000000000 --- a/src/isl/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/isl_format_layout.c diff --git a/src/isl/Makefile.am b/src/isl/Makefile.am deleted file mode 100644 index 72f5460554f..00000000000 --- a/src/isl/Makefile.am +++ /dev/null @@ -1,90 +0,0 @@ -# Copyright 2015 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. - -SUBDIRS = . - -noinst_LTLIBRARIES = libisl.la - -EXTRA_DIST = tests - -# The gallium includes are for the util/u_math.h include from main/macros.h -AM_CPPFLAGS = \ - $(INTEL_CFLAGS) \ - $(VALGRIND_CFLAGS) \ - $(DEFINES) \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/src \ - -I$(top_srcdir)/src/mapi \ - -I$(top_srcdir)/src/mesa \ - -I$(top_srcdir)/src/mesa/drivers/dri/common \ - -I$(top_srcdir)/src/mesa/drivers/dri/i965 \ - -I$(top_srcdir)/src/gallium/auxiliary \ - -I$(top_srcdir)/src/gallium/include \ - -I$(top_builddir)/src - -libisl_la_CFLAGS = $(CFLAGS) -Wno-override-init - -libisl_la_SOURCES = \ - isl.c \ - isl.h \ - isl_format.c \ - isl_format_layout.c \ - isl_gen4.c \ - isl_gen4.h \ - isl_gen6.c \ - isl_gen6.h \ - isl_gen7.c \ - isl_gen7.h \ - isl_gen8.c \ - isl_gen8.h \ - isl_gen9.c \ - isl_gen9.h \ - isl_image.c \ - $(NULL) - -BUILT_SOURCES = \ - isl_format_layout.c - -isl_format_layout.c: isl_format_layout_gen.bash \ - isl_format_layout.csv - $(AM_V_GEN)$(srcdir)/isl_format_layout_gen.bash \ - <$(srcdir)/isl_format_layout.csv >$@ - -# ---------------------------------------------------------------------------- -# Tests -# ---------------------------------------------------------------------------- - -TESTS = tests/isl_surf_get_image_offset_test - -check_PROGRAMS = $(TESTS) - -# Link tests to lib965_compiler.la for brw_get_device_info(). -tests_ldadd = \ - libisl.la \ - $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la - -tests_isl_surf_get_image_offset_test_SOURCES = \ - tests/isl_surf_get_image_offset_test.c -tests_isl_surf_get_image_offset_test_LDADD = $(tests_ldadd) - -# ---------------------------------------------------------------------------- - -include $(top_srcdir)/install-lib-links.mk diff --git a/src/isl/README b/src/isl/README deleted file mode 100644 index 1ab4313fcc5..00000000000 --- a/src/isl/README +++ /dev/null @@ -1,113 +0,0 @@ -Intel Surface Layout - -Introduction -============ -isl is a small library that calculates the layout of Intel GPU surfaces, queries -those layouts, and queries the properties of surface formats. - - -Independence from User APIs -=========================== -isl's API is independent of any user-facing graphics API, such as OpenGL and -Vulkan. This independence allows isl to be used a shared component by multiple -Intel drivers. - -Rather than mimic the user-facing APIs, the isl API attempts to reflect Intel -hardware: the actual memory layout of Intel GPU surfaces and how one programs -the GPU to use those surfaces. For example: - - - The tokens of `enum isl_format` (such as `ISL_FORMAT_R8G8B8A8_UNORM`) - match those of the hardware enum `SURFACE_FORMAT` rather than the OpenGL - or Vulkan format tokens. And the values of `isl_format` and - `SURFACE_FORMAT` are identical. - - - The OpenGL and Vulkan APIs contain depth and stencil formats. However the - hardware enum `SURFACE_FORMAT` does not, and therefore neither does `enum - isl_format`. Rather than define new pixel formats that have no hardware - counterpart, isl records the intent to use a surface as a depth or stencil - buffer with the usage flags `ISL_SURF_USAGE_DEPTH_BIT` and - `ISL_SURF_USAGE_STENCIL_BIT`. - - - `struct isl_surf` distinguishes between the surface's logical dimension - from the user API's perspective (`enum isl_surf_dim`, which may be 1D, 2D, - or 3D) and the layout of those dimensions in memory (`enum isl_dim_layout`). - - -Surface Units -============= - -Intro ------ -ISL takes care in its equations to correctly handle conversion among surface -units (such as pixels and compression blocks) and to carefully distinguish -between a surface's logical layout in the client API and its physical layout -in memory. - -Symbol names often explicitly declare their unit with a suffix: - - - px: logical pixels - - sa: physical surface samples - - el: physical surface elements - - sa_rows: rows of physical surface samples - - el_rows: rows of physical surface elements - -Logical units are independent of hardware generation and are closely related -to the user-facing API (OpenGL and Vulkan). Physical units are dependent on -hardware generation and reflect the surface's layout in memory. - -Definitions ------------ -- Logical Pixels (px): - - The surface's layout from the perspective of the client API (OpenGL and - Vulkan) is in units of logical pixels. Logical pixels are independent of the - surface's layout in memory. - - A surface's width and height, in units of logical pixels, is not affected by - the surface's sample count. For example, consider a VkImage created with - VkImageCreateInfo{width=w0, height=h0, samples=s0}. The surface's width and - height at level 0 is, in units of logical pixels, w0 and h0 regardless of - the value of s0. - - For example, the logical array length of a 3D surface is always 1, even on - Gen9 where the surface's memory layout is that of an array surface - (ISL_DIM_LAYOUT_GEN4_2D). - -- Physical Surface Samples (sa): - - For a multisampled surface, this unit has the obvious meaning. - A singlesampled surface, from ISL's perspective, is simply a multisampled - surface whose sample count is 1. - - For example, consider a 2D single-level non-array surface with samples=4, - width_px=64, and height_px=64 (note that the suffix 'px' indicates logical - pixels). If the surface's multisample layout is ISL_MSAA_LAYOUT_INTERLEAVED, - then the extent of level 0 is, in units of physical surface samples, - width_sa=128, height_sa=128, depth_sa=1, array_length_sa=1. If - ISL_MSAA_LAYOUT_ARRAY, then width_sa=64, height_sa=64, depth_sa=1, - array_length_sa=4. - -- Physical Surface Elements (el): - - This unit allows ISL to treat compressed and uncompressed formats - identically in many calculations. - - If the surface's pixel format is compressed, such as ETC2, then a surface - element is equivalent to a compression block. If uncompressed, then - a surface element is equivalent to a surface sample. As a corollary, for - a given surface a surface element is at least as large as a surface sample. - -Errata ------- -ISL acquired the term 'surface element' from the Broadwell PRM [1], which -defines it as follows: - - An element is defined as a pixel in uncompresed surface formats, and as - a compression block in compressed surface formats. For MSFMT_DEPTH_STENCIL - type multisampled surfaces, an element is a sample. - - -References -========== -[1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >> - RENDER_SURFACE_STATE Surface Vertical Alignment (p325) diff --git a/src/isl/isl.c b/src/isl/isl.c deleted file mode 100644 index 27928fd0850..00000000000 --- a/src/isl/isl.c +++ /dev/null @@ -1,1428 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include - -#include "isl.h" -#include "isl_gen4.h" -#include "isl_gen6.h" -#include "isl_gen7.h" -#include "isl_gen8.h" -#include "isl_gen9.h" -#include "isl_priv.h" - -void PRINTFLIKE(3, 4) UNUSED -__isl_finishme(const char *file, int line, const char *fmt, ...) -{ - va_list ap; - char buf[512]; - - va_start(ap, fmt); - vsnprintf(buf, sizeof(buf), fmt, ap); - va_end(ap); - - fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); -} - -void -isl_device_init(struct isl_device *dev, - const struct brw_device_info *info, - bool has_bit6_swizzling) -{ - dev->info = info; - dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6; - dev->has_bit6_swizzling = has_bit6_swizzling; - - /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some - * device properties at buildtime. Verify that the macros with the device - * properties chosen during runtime. - */ - assert(ISL_DEV_GEN(dev) == dev->info->gen); - assert(ISL_DEV_USE_SEPARATE_STENCIL(dev) == dev->use_separate_stencil); - - /* Did we break hiz or stencil? */ - if (ISL_DEV_USE_SEPARATE_STENCIL(dev)) - assert(info->has_hiz_and_separate_stencil); - if (info->must_use_separate_stencil) - assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); -} - -/** - * @brief Query the set of multisamples supported by the device. - * - * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always - * supported. - */ -isl_sample_count_mask_t ATTRIBUTE_CONST -isl_device_get_sample_counts(struct isl_device *dev) -{ - if (ISL_DEV_GEN(dev) >= 9) { - return ISL_SAMPLE_COUNT_1_BIT | - ISL_SAMPLE_COUNT_2_BIT | - ISL_SAMPLE_COUNT_4_BIT | - ISL_SAMPLE_COUNT_8_BIT | - ISL_SAMPLE_COUNT_16_BIT; - } else if (ISL_DEV_GEN(dev) >= 8) { - return ISL_SAMPLE_COUNT_1_BIT | - ISL_SAMPLE_COUNT_2_BIT | - ISL_SAMPLE_COUNT_4_BIT | - ISL_SAMPLE_COUNT_8_BIT; - } else if (ISL_DEV_GEN(dev) >= 7) { - return ISL_SAMPLE_COUNT_1_BIT | - ISL_SAMPLE_COUNT_4_BIT | - ISL_SAMPLE_COUNT_8_BIT; - } else if (ISL_DEV_GEN(dev) >= 6) { - return ISL_SAMPLE_COUNT_1_BIT | - ISL_SAMPLE_COUNT_4_BIT; - } else { - return ISL_SAMPLE_COUNT_1_BIT; - } -} - -/** - * @param[out] info is written only on success - */ -bool -isl_tiling_get_info(const struct isl_device *dev, - enum isl_tiling tiling, - uint32_t format_block_size, - struct isl_tile_info *tile_info) -{ - const uint32_t bs = format_block_size; - uint32_t width, height; - - assert(bs > 0); - - switch (tiling) { - case ISL_TILING_LINEAR: - width = 1; - height = 1; - break; - - case ISL_TILING_X: - width = 1 << 9; - height = 1 << 3; - break; - - case ISL_TILING_Y0: - width = 1 << 7; - height = 1 << 5; - break; - - case ISL_TILING_W: - /* XXX: Should W tile be same as Y? */ - width = 1 << 6; - height = 1 << 6; - break; - - case ISL_TILING_Yf: - case ISL_TILING_Ys: { - if (ISL_DEV_GEN(dev) < 9) - return false; - - if (!isl_is_pow2(bs)) - return false; - - bool is_Ys = tiling == ISL_TILING_Ys; - - width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys)); - height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys)); - break; - } - } /* end switch */ - - *tile_info = (struct isl_tile_info) { - .tiling = tiling, - .width = width, - .height = height, - .size = width * height, - }; - - return true; -} - -void -isl_tiling_get_extent(const struct isl_device *dev, - enum isl_tiling tiling, - uint32_t format_block_size, - struct isl_extent2d *e) -{ - struct isl_tile_info tile_info; - isl_tiling_get_info(dev, tiling, format_block_size, &tile_info); - *e = isl_extent2d(tile_info.width, tile_info.height); -} - -/** - * @param[out] tiling is set only on success - */ -bool -isl_surf_choose_tiling(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling *tiling) -{ - isl_tiling_flags_t tiling_flags = info->tiling_flags; - - if (ISL_DEV_GEN(dev) >= 7) { - gen7_filter_tiling(dev, info, &tiling_flags); - } else { - isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev)); - gen7_filter_tiling(dev, info, &tiling_flags); - } - - #define CHOOSE(__tiling) \ - do { \ - if (tiling_flags & (1u << (__tiling))) { \ - *tiling = (__tiling); \ - return true; \ - } \ - } while (0) - - /* Of the tiling modes remaining, choose the one that offers the best - * performance. - */ - - if (info->dim == ISL_SURF_DIM_1D) { - /* Prefer linear for 1D surfaces because they do not benefit from - * tiling. To the contrary, tiling leads to wasted memory and poor - * memory locality due to the swizzling and alignment restrictions - * required in tiled surfaces. - */ - CHOOSE(ISL_TILING_LINEAR); - } - - CHOOSE(ISL_TILING_Ys); - CHOOSE(ISL_TILING_Yf); - CHOOSE(ISL_TILING_Y0); - CHOOSE(ISL_TILING_X); - CHOOSE(ISL_TILING_W); - CHOOSE(ISL_TILING_LINEAR); - - #undef CHOOSE - - /* No tiling mode accomodates the inputs. */ - return false; -} - -static bool -isl_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout) -{ - if (ISL_DEV_GEN(dev) >= 8) { - return gen8_choose_msaa_layout(dev, info, tiling, msaa_layout); - } else if (ISL_DEV_GEN(dev) >= 7) { - return gen7_choose_msaa_layout(dev, info, tiling, msaa_layout); - } else if (ISL_DEV_GEN(dev) >= 6) { - return gen6_choose_msaa_layout(dev, info, tiling, msaa_layout); - } else { - return gen4_choose_msaa_layout(dev, info, tiling, msaa_layout); - } -} - -static void -isl_msaa_interleaved_scale_px_to_sa(uint32_t samples, - uint32_t *width, uint32_t *height) -{ - assert(isl_is_pow2(samples)); - - /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level - * Sizes (p133): - * - * If the surface is multisampled and it is a depth or stencil surface - * or Multisampled Surface StorageFormat in SURFACE_STATE is - * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before - * proceeding: [...] - */ - if (width) - *width = isl_align(*width, 2) << ((ffs(samples) - 0) / 2); - if (height) - *height = isl_align(*height, 2) << ((ffs(samples) - 1) / 2); -} - -static enum isl_array_pitch_span -isl_choose_array_pitch_span(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_dim_layout dim_layout, - const struct isl_extent4d *phys_level0_sa) -{ - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - case ISL_DIM_LAYOUT_GEN4_2D: - if (ISL_DEV_GEN(dev) >= 8) { - /* QPitch becomes programmable in Broadwell. So choose the - * most compact QPitch possible in order to conserve memory. - * - * From the Broadwell PRM >> Volume 2d: Command Reference: Structures - * >> RENDER_SURFACE_STATE Surface QPitch (p325): - * - * - Software must ensure that this field is set to a value - * sufficiently large such that the array slices in the surface - * do not overlap. Refer to the Memory Data Formats section for - * information on how surfaces are stored in memory. - * - * - This field specifies the distance in rows between array - * slices. It is used only in the following cases: - * - * - Surface Array is enabled OR - * - Number of Mulitsamples is not NUMSAMPLES_1 and - * Multisampled Surface Storage Format set to MSFMT_MSS OR - * - Surface Type is SURFTYPE_CUBE - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } else if (ISL_DEV_GEN(dev) >= 7) { - /* Note that Ivybridge introduces - * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the - * driver more control over the QPitch. - */ - - if (phys_level0_sa->array_len == 1) { - /* The hardware will never use the QPitch. So choose the most - * compact QPitch possible in order to conserve memory. - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - if (isl_surf_usage_is_depth_or_stencil(info->usage)) { - /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >> - * Section 6.18.4.7: Surface Arrays (p112): - * - * If Surface Array Spacing is set to ARYSPC_FULL (note that - * the depth buffer and stencil buffer have an implied value of - * ARYSPC_FULL): - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - if (info->levels == 1) { - /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing - * to ARYSPC_LOD0. - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - return ISL_ARRAY_PITCH_SPAN_FULL; - } else if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && - ISL_DEV_USE_SEPARATE_STENCIL(dev) && - isl_surf_usage_is_stencil(info->usage)) { - /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: - * Graphics Core >> Section 7.18.3.7: Surface Arrays: - * - * The separate stencil buffer does not support mip mapping, thus - * the storage for LODs other than LOD 0 is not needed. - */ - assert(info->levels == 1); - assert(phys_level0_sa->array_len == 1); - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } else { - if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && - ISL_DEV_USE_SEPARATE_STENCIL(dev) && - isl_surf_usage_is_stencil(info->usage)) { - /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: - * Graphics Core >> Section 7.18.3.7: Surface Arrays: - * - * The separate stencil buffer does not support mip mapping, - * thus the storage for LODs other than LOD 0 is not needed. - */ - assert(info->levels == 1); - assert(phys_level0_sa->array_len == 1); - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - if (phys_level0_sa->array_len == 1) { - /* The hardware will never use the QPitch. So choose the most - * compact QPitch possible in order to conserve memory. - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - return ISL_ARRAY_PITCH_SPAN_FULL; - } - - case ISL_DIM_LAYOUT_GEN4_3D: - /* The hardware will never use the QPitch. So choose the most - * compact QPitch possible in order to conserve memory. - */ - return ISL_ARRAY_PITCH_SPAN_COMPACT; - } - - unreachable("bad isl_dim_layout"); - return ISL_ARRAY_PITCH_SPAN_FULL; -} - -static void -isl_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - if (ISL_DEV_GEN(dev) >= 9) { - gen9_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); - } else if (ISL_DEV_GEN(dev) >= 8) { - gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); - } else if (ISL_DEV_GEN(dev) >= 7) { - gen7_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); - } else if (ISL_DEV_GEN(dev) >= 6) { - gen6_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); - } else { - gen4_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); - } -} - -static enum isl_dim_layout -isl_surf_choose_dim_layout(const struct isl_device *dev, - enum isl_surf_dim logical_dim) -{ - if (ISL_DEV_GEN(dev) >= 9) { - switch (logical_dim) { - case ISL_SURF_DIM_1D: - return ISL_DIM_LAYOUT_GEN9_1D; - case ISL_SURF_DIM_2D: - case ISL_SURF_DIM_3D: - return ISL_DIM_LAYOUT_GEN4_2D; - } - } else { - switch (logical_dim) { - case ISL_SURF_DIM_1D: - case ISL_SURF_DIM_2D: - return ISL_DIM_LAYOUT_GEN4_2D; - case ISL_SURF_DIM_3D: - return ISL_DIM_LAYOUT_GEN4_3D; - } - } - - unreachable("bad isl_surf_dim"); - return ISL_DIM_LAYOUT_GEN4_2D; -} - -/** - * Calculate the physical extent of the surface's first level, in units of - * surface samples. The result is aligned to the format's compression block. - */ -static void -isl_calc_phys_level0_extent_sa(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_dim_layout dim_layout, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent4d *phys_level0_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - if (isl_format_is_yuv(info->format)) - isl_finishme("%s:%s: YUV format", __FILE__, __func__); - - switch (info->dim) { - case ISL_SURF_DIM_1D: - assert(info->height == 1); - assert(info->depth == 1); - assert(info->samples == 1); - assert(!isl_format_is_compressed(info->format)); - - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN4_3D: - unreachable("bad isl_dim_layout"); - - case ISL_DIM_LAYOUT_GEN9_1D: - case ISL_DIM_LAYOUT_GEN4_2D: - *phys_level0_sa = (struct isl_extent4d) { - .w = info->width, - .h = 1, - .d = 1, - .a = info->array_len, - }; - break; - } - break; - - case ISL_SURF_DIM_2D: - assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D); - - if (tiling == ISL_TILING_Ys && info->samples > 1) - isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__); - - switch (msaa_layout) { - case ISL_MSAA_LAYOUT_NONE: - assert(info->depth == 1); - assert(info->samples == 1); - - *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align(info->width, fmtl->bw), - .h = isl_align(info->height, fmtl->bh), - .d = 1, - .a = info->array_len, - }; - break; - - case ISL_MSAA_LAYOUT_ARRAY: - assert(info->depth == 1); - assert(info->array_len == 1); - assert(!isl_format_is_compressed(info->format)); - - *phys_level0_sa = (struct isl_extent4d) { - .w = info->width, - .h = info->height, - .d = 1, - .a = info->samples, - }; - break; - - case ISL_MSAA_LAYOUT_INTERLEAVED: - assert(info->depth == 1); - assert(info->array_len == 1); - assert(!isl_format_is_compressed(info->format)); - - *phys_level0_sa = (struct isl_extent4d) { - .w = info->width, - .h = info->height, - .d = 1, - .a = 1, - }; - - isl_msaa_interleaved_scale_px_to_sa(info->samples, - &phys_level0_sa->w, - &phys_level0_sa->h); - break; - } - break; - - case ISL_SURF_DIM_3D: - assert(info->array_len == 1); - assert(info->samples == 1); - - if (fmtl->bd > 1) { - isl_finishme("%s:%s: compression block with depth > 1", - __FILE__, __func__); - } - - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - unreachable("bad isl_dim_layout"); - - case ISL_DIM_LAYOUT_GEN4_2D: - assert(ISL_DEV_GEN(dev) >= 9); - - *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align(info->width, fmtl->bw), - .h = isl_align(info->height, fmtl->bh), - .d = 1, - .a = info->depth, - }; - break; - - case ISL_DIM_LAYOUT_GEN4_3D: - assert(ISL_DEV_GEN(dev) < 9); - *phys_level0_sa = (struct isl_extent4d) { - .w = isl_align(info->width, fmtl->bw), - .h = isl_align(info->height, fmtl->bh), - .d = info->depth, - .a = 1, - }; - break; - } - break; - } -} - -/** - * A variant of isl_calc_phys_slice0_extent_sa() specific to - * ISL_DIM_LAYOUT_GEN4_2D. - */ -static void -isl_calc_phys_slice0_extent_sa_gen4_2d( - const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_msaa_layout msaa_layout, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - assert(phys_level0_sa->depth == 1); - - if (info->levels == 1 && msaa_layout != ISL_MSAA_LAYOUT_INTERLEAVED) { - /* Do not pad the surface to the image alignment. Instead, pad it only - * to the pixel format's block alignment. - * - * For tiled surfaces, using a reduced alignment here avoids wasting CPU - * cycles on the below mipmap layout caluclations. Reducing the - * alignment here is safe because we later align the row pitch and array - * pitch to the tile boundary. It is safe even for - * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled - * to accomodate the interleaved samples. - * - * For linear surfaces, reducing the alignment here permits us to later - * choose an arbitrary, non-aligned row pitch. If the surface backs - * a VkBuffer, then an arbitrary pitch may be needed to accomodate - * VkBufferImageCopy::bufferRowLength. - */ - *phys_slice0_sa = (struct isl_extent2d) { - .w = isl_align_npot(phys_level0_sa->w, fmtl->bw), - .h = isl_align_npot(phys_level0_sa->h, fmtl->bh), - }; - return; - } - - uint32_t slice_top_w = 0; - uint32_t slice_bottom_w = 0; - uint32_t slice_left_h = 0; - uint32_t slice_right_h = 0; - - uint32_t W0 = phys_level0_sa->w; - uint32_t H0 = phys_level0_sa->h; - - for (uint32_t l = 0; l < info->levels; ++l) { - uint32_t W = isl_minify(W0, l); - uint32_t H = isl_minify(H0, l); - - if (msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { - /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level - * Sizes (p133): - * - * If the surface is multisampled and it is a depth or stencil - * surface or Multisampled Surface StorageFormat in - * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be - * adjusted as follows before proceeding: [...] - */ - isl_msaa_interleaved_scale_px_to_sa(info->samples, &W, &H); - } - - uint32_t w = isl_align_npot(W, image_align_sa->w); - uint32_t h = isl_align_npot(H, image_align_sa->h); - - if (l == 0) { - slice_top_w = w; - slice_left_h = h; - slice_right_h = h; - } else if (l == 1) { - slice_bottom_w = w; - slice_left_h += h; - } else if (l == 2) { - slice_bottom_w += w; - slice_right_h += h; - } else { - slice_right_h += h; - } - } - - *phys_slice0_sa = (struct isl_extent2d) { - .w = MAX(slice_top_w, slice_bottom_w), - .h = MAX(slice_left_h, slice_right_h), - }; -} - -/** - * A variant of isl_calc_phys_slice0_extent_sa() specific to - * ISL_DIM_LAYOUT_GEN4_3D. - */ -static void -isl_calc_phys_slice0_extent_sa_gen4_3d( - const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) -{ - assert(info->samples == 1); - assert(phys_level0_sa->array_len == 1); - - uint32_t slice_w = 0; - uint32_t slice_h = 0; - - uint32_t W0 = phys_level0_sa->w; - uint32_t H0 = phys_level0_sa->h; - uint32_t D0 = phys_level0_sa->d; - - for (uint32_t l = 0; l < info->levels; ++l) { - uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); - uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h); - uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d); - - uint32_t max_layers_horiz = MIN(level_d, 1u << l); - uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); - - slice_w = MAX(slice_w, level_w * max_layers_horiz); - slice_h += level_h * max_layers_vert; - } - - *phys_slice0_sa = (struct isl_extent2d) { - .w = slice_w, - .h = slice_h, - }; -} - -/** - * A variant of isl_calc_phys_slice0_extent_sa() specific to - * ISL_DIM_LAYOUT_GEN9_1D. - */ -static void -isl_calc_phys_slice0_extent_sa_gen9_1d( - const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - assert(phys_level0_sa->height == 1); - assert(phys_level0_sa->depth == 1); - assert(info->samples == 1); - assert(image_align_sa->w >= fmtl->bw); - - uint32_t slice_w = 0; - const uint32_t W0 = phys_level0_sa->w; - - for (uint32_t l = 0; l < info->levels; ++l) { - uint32_t W = isl_minify(W0, l); - uint32_t w = isl_align_npot(W, image_align_sa->w); - - slice_w += w; - } - - *phys_slice0_sa = isl_extent2d(slice_w, 1); -} - -/** - * Calculate the physical extent of the surface's first array slice, in units - * of surface samples. If the surface is multi-leveled, then the result will - * be aligned to \a image_align_sa. - */ -static void -isl_calc_phys_slice0_extent_sa(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_dim_layout dim_layout, - enum isl_msaa_layout msaa_layout, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - struct isl_extent2d *phys_slice0_sa) -{ - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info, - image_align_sa, phys_level0_sa, - phys_slice0_sa); - return; - case ISL_DIM_LAYOUT_GEN4_2D: - isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, - image_align_sa, phys_level0_sa, - phys_slice0_sa); - return; - case ISL_DIM_LAYOUT_GEN4_3D: - isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa, - phys_level0_sa, phys_slice0_sa); - return; - } -} - -/** - * Calculate the pitch between physical array slices, in units of rows of - * surface elements. - */ -static uint32_t -isl_calc_array_pitch_el_rows(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_tile_info *tile_info, - enum isl_dim_layout dim_layout, - enum isl_array_pitch_span array_pitch_span, - const struct isl_extent3d *image_align_sa, - const struct isl_extent4d *phys_level0_sa, - const struct isl_extent2d *phys_slice0_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - uint32_t pitch_sa_rows = 0; - - switch (dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - /* Each row is an array slice */ - pitch_sa_rows = 1; - break; - case ISL_DIM_LAYOUT_GEN4_2D: - switch (array_pitch_span) { - case ISL_ARRAY_PITCH_SPAN_COMPACT: - pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); - break; - case ISL_ARRAY_PITCH_SPAN_FULL: { - /* The QPitch equation is found in the Broadwell PRM >> Volume 5: - * Memory Views >> Common Surface Formats >> Surface Layout >> 2D - * Surfaces >> Surface Arrays. - */ - uint32_t H0_sa = phys_level0_sa->h; - uint32_t H1_sa = isl_minify(H0_sa, 1); - - uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h); - uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h); - - uint32_t m; - if (ISL_DEV_GEN(dev) >= 7) { - /* The QPitch equation changed slightly in Ivybridge. */ - m = 12; - } else { - m = 11; - } - - pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h); - - if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 && - (info->height % 4 == 1)) { - /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: - * Graphics Core >> Section 7.18.3.7: Surface Arrays: - * - * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than - * the value calculated in the equation above , for every - * other odd Surface Height starting from 1 i.e. 1,5,9,13. - * - * XXX(chadv): Is the errata natural corollary of the physical - * layout of interleaved samples? - */ - pitch_sa_rows += 4; - } - - pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh); - } /* end case */ - break; - } - break; - case ISL_DIM_LAYOUT_GEN4_3D: - assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); - pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); - break; - default: - unreachable("bad isl_dim_layout"); - break; - } - - assert(pitch_sa_rows % fmtl->bh == 0); - uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; - - if (ISL_DEV_GEN(dev) >= 9 && - info->dim == ISL_SURF_DIM_3D && - tile_info->tiling != ISL_TILING_LINEAR) { - /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch: - * - * Tile Mode != Linear: This field must be set to an integer multiple - * of the tile height - */ - pitch_el_rows = isl_align(pitch_el_rows, tile_info->height); - } - - return pitch_el_rows; -} - -/** - * Calculate the pitch of each surface row, in bytes. - */ -static uint32_t -isl_calc_row_pitch(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_tile_info *tile_info, - const struct isl_extent3d *image_align_sa, - const struct isl_extent2d *phys_slice0_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - uint32_t row_pitch = info->min_pitch; - - /* First, align the surface to a cache line boundary, as the PRM explains - * below. - * - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Render Target and Media - * Surfaces: - * - * The data port accesses data (pixels) outside of the surface if they - * are contained in the same cache request as pixels that are within the - * surface. These pixels will not be returned by the requesting message, - * however if these pixels lie outside of defined pages in the GTT, - * a GTT error will result when the cache request is processed. In order - * to avoid these GTT errors, “padding” at the bottom of the surface is - * sometimes necessary. - * - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: - * - * The sampling engine accesses texels outside of the surface if they - * are contained in the same cache line as texels that are within the - * surface. These texels will not participate in any calculation - * performed by the sampling engine and will not affect the result of - * any sampling engine operation, however if these texels lie outside of - * defined pages in the GTT, a GTT error will result when the cache line - * is accessed. In order to avoid these GTT errors, “padding” at the - * bottom and right side of a sampling engine surface is sometimes - * necessary. - * - * It is possible that a cache line will straddle a page boundary if the - * base address or pitch is not aligned. All pages included in the cache - * lines that are part of the surface must map to valid GTT entries to - * avoid errors. To determine the necessary padding on the bottom and - * right side of the surface, refer to the table in Alignment Unit Size - * section for the i and j parameters for the surface format in use. The - * surface must then be extended to the next multiple of the alignment - * unit size in each dimension, and all texels contained in this - * extended surface must have valid GTT entries. - * - * For example, suppose the surface size is 15 texels by 10 texels and - * the alignment parameters are i=4 and j=2. In this case, the extended - * surface would be 16 by 10. Note that these calculations are done in - * texels, and must be converted to bytes based on the surface format - * being used to determine whether additional pages need to be defined. - */ - assert(phys_slice0_sa->w % fmtl->bw == 0); - row_pitch = MAX(row_pitch, fmtl->bs * (phys_slice0_sa->w / fmtl->bw)); - - switch (tile_info->tiling) { - case ISL_TILING_LINEAR: - /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> - * RENDER_SURFACE_STATE Surface Pitch (p349): - * - * - For linear render target surfaces and surfaces accessed with the - * typed data port messages, the pitch must be a multiple of the - * element size for non-YUV surface formats. Pitch must be - * a multiple of 2 * element size for YUV surface formats. - * - * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we - * ignore because isl doesn't do buffers.] - * - * - For other linear surfaces, the pitch can be any multiple of - * bytes. - */ - if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { - if (isl_format_is_yuv(info->format)) { - row_pitch = isl_align_npot(row_pitch, 2 * fmtl->bs); - } else { - row_pitch = isl_align_npot(row_pitch, fmtl->bs); - } - } - break; - default: - /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> - * RENDER_SURFACE_STATE Surface Pitch (p349): - * - * - For tiled surfaces, the pitch must be a multiple of the tile - * width. - */ - row_pitch = isl_align(row_pitch, tile_info->width); - break; - } - - return row_pitch; -} - -/** - * Calculate the surface's total height, including padding, in units of - * surface elements. - */ -static uint32_t -isl_calc_total_height_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - const struct isl_tile_info *tile_info, - uint32_t phys_array_len, - uint32_t row_pitch, - uint32_t array_pitch_el_rows) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - uint32_t total_h_el = phys_array_len * array_pitch_el_rows; - uint32_t pad_bytes = 0; - - /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Render Target and Media - * Surfaces: - * - * The data port accesses data (pixels) outside of the surface if they - * are contained in the same cache request as pixels that are within the - * surface. These pixels will not be returned by the requesting message, - * however if these pixels lie outside of defined pages in the GTT, - * a GTT error will result when the cache request is processed. In - * order to avoid these GTT errors, “padding” at the bottom of the - * surface is sometimes necessary. - * - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface - * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: - * - * ... Lots of padding requirements, all listed separately below. - */ - - /* We can safely ignore the first padding requirement, quoted below, - * because isl doesn't do buffers. - * - * - [pre-BDW] For buffers, which have no inherent “height,” padding - * requirements are different. A buffer must be padded to the next - * multiple of 256 array elements, with an additional 16 bytes added - * beyond that to account for the L1 cache line. - */ - - /* - * - For compressed textures [...], padding at the bottom of the surface - * is to an even compressed row. - */ - if (isl_format_is_compressed(info->format)) - total_h_el = isl_align(total_h_el, 2); - - /* - * - For cube surfaces, an additional two rows of padding are required - * at the bottom of the surface. - */ - if (info->usage & ISL_SURF_USAGE_CUBE_BIT) - total_h_el += 2; - - /* - * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats, - * additional padding is required. These surfaces require an extra row - * plus 16 bytes of padding at the bottom in addition to the general - * padding requirements. - */ - if (isl_format_is_yuv(info->format) && - (fmtl->bs == 96 || fmtl->bs == 48|| fmtl->bs == 24)) { - total_h_el += 1; - pad_bytes += 16; - } - - /* - * - For linear surfaces, additional padding of 64 bytes is required at - * the bottom of the surface. This is in addition to the padding - * required above. - */ - if (tile_info->tiling == ISL_TILING_LINEAR) - pad_bytes += 64; - - /* The below text weakens, not strengthens, the padding requirements for - * linear surfaces. Therefore we can safely ignore it. - * - * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array, - * non-MSAA, non-mip-mapped surfaces in linear memory, the only - * padding requirement is to the next aligned 64-byte boundary beyond - * the end of the surface. The rest of the padding requirements - * documented above do not apply to these surfaces. - */ - - /* - * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and - * height % 4 != 0, the surface must be padded with - * 4-(height % 4)*Surface Pitch # of bytes. - */ - if (ISL_DEV_GEN(dev) >= 9 && - tile_info->tiling == ISL_TILING_LINEAR && - (info->dim == ISL_SURF_DIM_2D || info->dim == ISL_SURF_DIM_3D)) { - total_h_el = isl_align(total_h_el, 4); - } - - /* - * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded - * to 4 times the Surface Pitch # of bytes - */ - if (ISL_DEV_GEN(dev) >= 9 && - tile_info->tiling == ISL_TILING_LINEAR && - info->dim == ISL_SURF_DIM_1D) { - total_h_el += 4; - } - - /* Be sloppy. Align any leftover padding to a row boundary. */ - total_h_el += isl_align_div_npot(pad_bytes, row_pitch); - - return total_h_el; -} - -bool -isl_surf_init_s(const struct isl_device *dev, - struct isl_surf *surf, - const struct isl_surf_init_info *restrict info) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - const struct isl_extent4d logical_level0_px = { - .w = info->width, - .h = info->height, - .d = info->depth, - .a = info->array_len, - }; - - enum isl_dim_layout dim_layout = - isl_surf_choose_dim_layout(dev, info->dim); - - enum isl_tiling tiling; - if (!isl_surf_choose_tiling(dev, info, &tiling)) - return false; - - struct isl_tile_info tile_info; - if (!isl_tiling_get_info(dev, tiling, fmtl->bs, &tile_info)) - return false; - - enum isl_msaa_layout msaa_layout; - if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout)) - return false; - - struct isl_extent3d image_align_el; - isl_choose_image_alignment_el(dev, info, tiling, msaa_layout, - &image_align_el); - - struct isl_extent3d image_align_sa = - isl_extent3d_el_to_sa(info->format, image_align_el); - - struct isl_extent4d phys_level0_sa; - isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout, - &phys_level0_sa); - assert(phys_level0_sa.w % fmtl->bw == 0); - assert(phys_level0_sa.h % fmtl->bh == 0); - - enum isl_array_pitch_span array_pitch_span = - isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa); - - struct isl_extent2d phys_slice0_sa; - isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout, - &image_align_sa, &phys_level0_sa, - &phys_slice0_sa); - assert(phys_slice0_sa.w % fmtl->bw == 0); - assert(phys_slice0_sa.h % fmtl->bh == 0); - - const uint32_t row_pitch = isl_calc_row_pitch(dev, info, &tile_info, - &image_align_sa, - &phys_slice0_sa); - - const uint32_t array_pitch_el_rows = - isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout, - array_pitch_span, &image_align_sa, - &phys_level0_sa, &phys_slice0_sa); - - const uint32_t total_h_el = - isl_calc_total_height_el(dev, info, &tile_info, - phys_level0_sa.array_len, row_pitch, - array_pitch_el_rows); - - const uint32_t total_h_sa = total_h_el * fmtl->bh; - const uint32_t size = row_pitch * isl_align(total_h_sa, tile_info.height); - - /* Alignment of surface base address, in bytes */ - uint32_t base_alignment = MAX(1, info->min_alignment); - assert(isl_is_pow2(base_alignment) && isl_is_pow2(tile_info.size)); - base_alignment = MAX(base_alignment, tile_info.size); - - *surf = (struct isl_surf) { - .dim = info->dim, - .dim_layout = dim_layout, - .msaa_layout = msaa_layout, - .tiling = tiling, - .format = info->format, - - .levels = info->levels, - .samples = info->samples, - - .image_alignment_el = image_align_el, - .logical_level0_px = logical_level0_px, - .phys_level0_sa = phys_level0_sa, - - .size = size, - .alignment = base_alignment, - .row_pitch = row_pitch, - .array_pitch_el_rows = array_pitch_el_rows, - .array_pitch_span = array_pitch_span, - - .usage = info->usage, - }; - - return true; -} - -void -isl_surf_get_tile_info(const struct isl_device *dev, - const struct isl_surf *surf, - struct isl_tile_info *tile_info) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - isl_tiling_get_info(dev, surf->tiling, fmtl->bs, tile_info); -} - -/** - * A variant of isl_surf_get_image_offset_sa() specific to - * ISL_DIM_LAYOUT_GEN4_2D. - */ -static void -get_image_offset_sa_gen4_2d(const struct isl_surf *surf, - uint32_t level, uint32_t layer, - uint32_t *x_offset_sa, - uint32_t *y_offset_sa) -{ - assert(level < surf->levels); - assert(layer < surf->phys_level0_sa.array_len); - assert(surf->phys_level0_sa.depth == 1); - - const struct isl_extent3d image_align_sa = - isl_surf_get_image_alignment_sa(surf); - - const uint32_t W0 = surf->phys_level0_sa.width; - const uint32_t H0 = surf->phys_level0_sa.height; - - uint32_t x = 0; - uint32_t y = layer * isl_surf_get_array_pitch_sa_rows(surf); - - for (uint32_t l = 0; l < level; ++l) { - if (l == 1) { - uint32_t W = isl_minify(W0, l); - - if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) - isl_msaa_interleaved_scale_px_to_sa(surf->samples, &W, NULL); - - x += isl_align_npot(W, image_align_sa.w); - } else { - uint32_t H = isl_minify(H0, l); - - if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) - isl_msaa_interleaved_scale_px_to_sa(surf->samples, NULL, &H); - - y += isl_align_npot(H, image_align_sa.h); - } - } - - *x_offset_sa = x; - *y_offset_sa = y; -} - -/** - * A variant of isl_surf_get_image_offset_sa() specific to - * ISL_DIM_LAYOUT_GEN4_3D. - */ -static void -get_image_offset_sa_gen4_3d(const struct isl_surf *surf, - uint32_t level, uint32_t logical_z_offset_px, - uint32_t *x_offset_sa, - uint32_t *y_offset_sa) -{ - assert(level < surf->levels); - assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level)); - assert(surf->phys_level0_sa.array_len == 1); - - const struct isl_extent3d image_align_sa = - isl_surf_get_image_alignment_sa(surf); - - const uint32_t W0 = surf->phys_level0_sa.width; - const uint32_t H0 = surf->phys_level0_sa.height; - const uint32_t D0 = surf->phys_level0_sa.depth; - - uint32_t x = 0; - uint32_t y = 0; - - for (uint32_t l = 0; l < level; ++l) { - const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h); - const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d); - const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); - - y += level_h * max_layers_vert; - } - - const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w); - const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h); - const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d); - - const uint32_t max_layers_horiz = MIN(level_d, 1u << level); - - x += level_w * (logical_z_offset_px % max_layers_horiz); - y += level_h * (logical_z_offset_px / max_layers_horiz); - - *x_offset_sa = x; - *y_offset_sa = y; -} - -/** - * A variant of isl_surf_get_image_offset_sa() specific to - * ISL_DIM_LAYOUT_GEN9_1D. - */ -static void -get_image_offset_sa_gen9_1d(const struct isl_surf *surf, - uint32_t level, uint32_t layer, - uint32_t *x_offset_sa, - uint32_t *y_offset_sa) -{ - assert(level < surf->levels); - assert(layer < surf->phys_level0_sa.array_len); - assert(surf->phys_level0_sa.height == 1); - assert(surf->phys_level0_sa.depth == 1); - assert(surf->samples == 1); - - const uint32_t W0 = surf->phys_level0_sa.width; - const struct isl_extent3d image_align_sa = - isl_surf_get_image_alignment_sa(surf); - - uint32_t x = 0; - - for (uint32_t l = 0; l < level; ++l) { - uint32_t W = isl_minify(W0, l); - uint32_t w = isl_align_npot(W, image_align_sa.w); - - x += w; - } - - *x_offset_sa = x; - *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf); -} - -/** - * Calculate the offset, in units of surface samples, to a subimage in the - * surface. - * - * @invariant level < surface levels - * @invariant logical_array_layer < logical array length of surface - * @invariant logical_z_offset_px < logical depth of surface at level - */ -static void -get_image_offset_sa(const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset_px, - uint32_t *x_offset_sa, - uint32_t *y_offset_sa) -{ - assert(level < surf->levels); - assert(logical_array_layer < surf->logical_level0_px.array_len); - assert(logical_z_offset_px - < isl_minify(surf->logical_level0_px.depth, level)); - - switch (surf->dim_layout) { - case ISL_DIM_LAYOUT_GEN9_1D: - get_image_offset_sa_gen9_1d(surf, level, logical_array_layer, - x_offset_sa, y_offset_sa); - break; - case ISL_DIM_LAYOUT_GEN4_2D: - get_image_offset_sa_gen4_2d(surf, level, logical_array_layer - + logical_z_offset_px, - x_offset_sa, y_offset_sa); - break; - case ISL_DIM_LAYOUT_GEN4_3D: - get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px, - x_offset_sa, y_offset_sa); - break; - } -} - -void -isl_surf_get_image_offset_el(const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset_px, - uint32_t *x_offset_el, - uint32_t *y_offset_el) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - - assert(level < surf->levels); - assert(logical_array_layer < surf->logical_level0_px.array_len); - assert(logical_z_offset_px - < isl_minify(surf->logical_level0_px.depth, level)); - - uint32_t x_offset_sa, y_offset_sa; - get_image_offset_sa(surf, level, - logical_array_layer, - logical_z_offset_px, - &x_offset_sa, - &y_offset_sa); - - *x_offset_el = x_offset_sa / fmtl->bw; - *y_offset_el = y_offset_sa / fmtl->bh; -} - -void -isl_surf_get_image_intratile_offset_el(const struct isl_device *dev, - const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset, - uint32_t *base_address_offset, - uint32_t *x_offset_el, - uint32_t *y_offset_el) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - - struct isl_tile_info tile_info; - isl_surf_get_tile_info(dev, surf, &tile_info); - - uint32_t total_x_offset_el; - uint32_t total_y_offset_el; - isl_surf_get_image_offset_el(surf, level, - logical_array_layer, - logical_z_offset, - &total_x_offset_el, - &total_y_offset_el); - - uint32_t small_y_offset_el = total_y_offset_el % tile_info.height; - uint32_t big_y_offset_el = total_y_offset_el - small_y_offset_el; - uint32_t big_y_offset_B = big_y_offset_el * surf->row_pitch; - - uint32_t total_x_offset_B = total_x_offset_el * fmtl->bs; - uint32_t small_x_offset_B = total_x_offset_B % tile_info.width; - uint32_t small_x_offset_el = small_x_offset_B / fmtl->bs; - uint32_t big_x_offset_B = total_x_offset_B - small_x_offset_B; - - *base_address_offset = big_y_offset_B + big_x_offset_B; - *x_offset_el = small_x_offset_el; - *y_offset_el = small_y_offset_el; -} - -uint32_t -isl_surf_get_depth_format(const struct isl_device *dev, - const struct isl_surf *surf) -{ - /* Support for separate stencil buffers began in gen5. Support for - * interleaved depthstencil buffers ceased in gen7. The intermediate gens, - * those that supported separate and interleaved stencil, were gen5 and - * gen6. - * - * For a list of all available formats, see the Sandybridge PRM >> Volume - * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface - * Format (p321). - */ - - bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT; - - assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT); - - if (has_stencil) - assert(ISL_DEV_GEN(dev) < 7); - - switch (surf->format) { - default: - unreachable("bad isl depth format"); - case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: - assert(ISL_DEV_GEN(dev) < 7); - return 0; /* D32_FLOAT_S8X24_UINT */ - case ISL_FORMAT_R32_FLOAT: - assert(!has_stencil); - return 1; /* D32_FLOAT */ - case ISL_FORMAT_R24_UNORM_X8_TYPELESS: - if (has_stencil) { - assert(ISL_DEV_GEN(dev) < 7); - return 2; /* D24_UNORM_S8_UINT */ - } else { - assert(ISL_DEV_GEN(dev) >= 5); - return 3; /* D24_UNORM_X8_UINT */ - } - case ISL_FORMAT_R16_UNORM: - assert(!has_stencil); - return 5; /* D16_UNORM */ - } -} diff --git a/src/isl/isl.h b/src/isl/isl.h deleted file mode 100644 index 3e0ff935948..00000000000 --- a/src/isl/isl.h +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -/** - * @file - * @brief Intel Surface Layout - * - * Header Layout - * ------------- - * The header is ordered as: - * - forward declarations - * - macros that may be overridden at compile-time for specific gens - * - enums and constants - * - structs and unions - * - functions - */ - -#pragma once - -#include -#include -#include - -#include "util/macros.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct brw_device_info; -struct brw_image_param; - -#ifndef ISL_DEV_GEN -/** - * @brief Get the hardware generation of isl_device. - * - * You can define this as a compile-time constant in the CFLAGS. For example, - * `gcc -DISL_DEV_GEN(dev)=9 ...`. - */ -#define ISL_DEV_GEN(__dev) ((__dev)->info->gen) -#endif - -#ifndef ISL_DEV_USE_SEPARATE_STENCIL -/** - * You can define this as a compile-time constant in the CFLAGS. For example, - * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`. - */ -#define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil) -#endif - -/** - * Hardware enumeration SURFACE_FORMAT. - * - * For the official list, see Broadwell PRM: Volume 2b: Command Reference: - * Enumerations: SURFACE_FORMAT. - */ -enum isl_format { - ISL_FORMAT_R32G32B32A32_FLOAT = 0, - ISL_FORMAT_R32G32B32A32_SINT = 1, - ISL_FORMAT_R32G32B32A32_UINT = 2, - ISL_FORMAT_R32G32B32A32_UNORM = 3, - ISL_FORMAT_R32G32B32A32_SNORM = 4, - ISL_FORMAT_R64G64_FLOAT = 5, - ISL_FORMAT_R32G32B32X32_FLOAT = 6, - ISL_FORMAT_R32G32B32A32_SSCALED = 7, - ISL_FORMAT_R32G32B32A32_USCALED = 8, - ISL_FORMAT_R32G32B32A32_SFIXED = 32, - ISL_FORMAT_R64G64_PASSTHRU = 33, - ISL_FORMAT_R32G32B32_FLOAT = 64, - ISL_FORMAT_R32G32B32_SINT = 65, - ISL_FORMAT_R32G32B32_UINT = 66, - ISL_FORMAT_R32G32B32_UNORM = 67, - ISL_FORMAT_R32G32B32_SNORM = 68, - ISL_FORMAT_R32G32B32_SSCALED = 69, - ISL_FORMAT_R32G32B32_USCALED = 70, - ISL_FORMAT_R32G32B32_SFIXED = 80, - ISL_FORMAT_R16G16B16A16_UNORM = 128, - ISL_FORMAT_R16G16B16A16_SNORM = 129, - ISL_FORMAT_R16G16B16A16_SINT = 130, - ISL_FORMAT_R16G16B16A16_UINT = 131, - ISL_FORMAT_R16G16B16A16_FLOAT = 132, - ISL_FORMAT_R32G32_FLOAT = 133, - ISL_FORMAT_R32G32_SINT = 134, - ISL_FORMAT_R32G32_UINT = 135, - ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136, - ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137, - ISL_FORMAT_L32A32_FLOAT = 138, - ISL_FORMAT_R32G32_UNORM = 139, - ISL_FORMAT_R32G32_SNORM = 140, - ISL_FORMAT_R64_FLOAT = 141, - ISL_FORMAT_R16G16B16X16_UNORM = 142, - ISL_FORMAT_R16G16B16X16_FLOAT = 143, - ISL_FORMAT_A32X32_FLOAT = 144, - ISL_FORMAT_L32X32_FLOAT = 145, - ISL_FORMAT_I32X32_FLOAT = 146, - ISL_FORMAT_R16G16B16A16_SSCALED = 147, - ISL_FORMAT_R16G16B16A16_USCALED = 148, - ISL_FORMAT_R32G32_SSCALED = 149, - ISL_FORMAT_R32G32_USCALED = 150, - ISL_FORMAT_R32G32_SFIXED = 160, - ISL_FORMAT_R64_PASSTHRU = 161, - ISL_FORMAT_B8G8R8A8_UNORM = 192, - ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193, - ISL_FORMAT_R10G10B10A2_UNORM = 194, - ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195, - ISL_FORMAT_R10G10B10A2_UINT = 196, - ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197, - ISL_FORMAT_R8G8B8A8_UNORM = 199, - ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200, - ISL_FORMAT_R8G8B8A8_SNORM = 201, - ISL_FORMAT_R8G8B8A8_SINT = 202, - ISL_FORMAT_R8G8B8A8_UINT = 203, - ISL_FORMAT_R16G16_UNORM = 204, - ISL_FORMAT_R16G16_SNORM = 205, - ISL_FORMAT_R16G16_SINT = 206, - ISL_FORMAT_R16G16_UINT = 207, - ISL_FORMAT_R16G16_FLOAT = 208, - ISL_FORMAT_B10G10R10A2_UNORM = 209, - ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210, - ISL_FORMAT_R11G11B10_FLOAT = 211, - ISL_FORMAT_R32_SINT = 214, - ISL_FORMAT_R32_UINT = 215, - ISL_FORMAT_R32_FLOAT = 216, - ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217, - ISL_FORMAT_X24_TYPELESS_G8_UINT = 218, - ISL_FORMAT_L32_UNORM = 221, - ISL_FORMAT_A32_UNORM = 222, - ISL_FORMAT_L16A16_UNORM = 223, - ISL_FORMAT_I24X8_UNORM = 224, - ISL_FORMAT_L24X8_UNORM = 225, - ISL_FORMAT_A24X8_UNORM = 226, - ISL_FORMAT_I32_FLOAT = 227, - ISL_FORMAT_L32_FLOAT = 228, - ISL_FORMAT_A32_FLOAT = 229, - ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230, - ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231, - ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232, - ISL_FORMAT_B8G8R8X8_UNORM = 233, - ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234, - ISL_FORMAT_R8G8B8X8_UNORM = 235, - ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236, - ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237, - ISL_FORMAT_B10G10R10X2_UNORM = 238, - ISL_FORMAT_L16A16_FLOAT = 240, - ISL_FORMAT_R32_UNORM = 241, - ISL_FORMAT_R32_SNORM = 242, - ISL_FORMAT_R10G10B10X2_USCALED = 243, - ISL_FORMAT_R8G8B8A8_SSCALED = 244, - ISL_FORMAT_R8G8B8A8_USCALED = 245, - ISL_FORMAT_R16G16_SSCALED = 246, - ISL_FORMAT_R16G16_USCALED = 247, - ISL_FORMAT_R32_SSCALED = 248, - ISL_FORMAT_R32_USCALED = 249, - ISL_FORMAT_B5G6R5_UNORM = 256, - ISL_FORMAT_B5G6R5_UNORM_SRGB = 257, - ISL_FORMAT_B5G5R5A1_UNORM = 258, - ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259, - ISL_FORMAT_B4G4R4A4_UNORM = 260, - ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261, - ISL_FORMAT_R8G8_UNORM = 262, - ISL_FORMAT_R8G8_SNORM = 263, - ISL_FORMAT_R8G8_SINT = 264, - ISL_FORMAT_R8G8_UINT = 265, - ISL_FORMAT_R16_UNORM = 266, - ISL_FORMAT_R16_SNORM = 267, - ISL_FORMAT_R16_SINT = 268, - ISL_FORMAT_R16_UINT = 269, - ISL_FORMAT_R16_FLOAT = 270, - ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271, - ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272, - ISL_FORMAT_I16_UNORM = 273, - ISL_FORMAT_L16_UNORM = 274, - ISL_FORMAT_A16_UNORM = 275, - ISL_FORMAT_L8A8_UNORM = 276, - ISL_FORMAT_I16_FLOAT = 277, - ISL_FORMAT_L16_FLOAT = 278, - ISL_FORMAT_A16_FLOAT = 279, - ISL_FORMAT_L8A8_UNORM_SRGB = 280, - ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281, - ISL_FORMAT_B5G5R5X1_UNORM = 282, - ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283, - ISL_FORMAT_R8G8_SSCALED = 284, - ISL_FORMAT_R8G8_USCALED = 285, - ISL_FORMAT_R16_SSCALED = 286, - ISL_FORMAT_R16_USCALED = 287, - ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290, - ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291, - ISL_FORMAT_A1B5G5R5_UNORM = 292, - ISL_FORMAT_A4B4G4R4_UNORM = 293, - ISL_FORMAT_L8A8_UINT = 294, - ISL_FORMAT_L8A8_SINT = 295, - ISL_FORMAT_R8_UNORM = 320, - ISL_FORMAT_R8_SNORM = 321, - ISL_FORMAT_R8_SINT = 322, - ISL_FORMAT_R8_UINT = 323, - ISL_FORMAT_A8_UNORM = 324, - ISL_FORMAT_I8_UNORM = 325, - ISL_FORMAT_L8_UNORM = 326, - ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327, - ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328, - ISL_FORMAT_R8_SSCALED = 329, - ISL_FORMAT_R8_USCALED = 330, - ISL_FORMAT_P8_UNORM_PALETTE0 = 331, - ISL_FORMAT_L8_UNORM_SRGB = 332, - ISL_FORMAT_P8_UNORM_PALETTE1 = 333, - ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334, - ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335, - ISL_FORMAT_Y8_UNORM = 336, - ISL_FORMAT_L8_UINT = 338, - ISL_FORMAT_L8_SINT = 339, - ISL_FORMAT_I8_UINT = 340, - ISL_FORMAT_I8_SINT = 341, - ISL_FORMAT_DXT1_RGB_SRGB = 384, - ISL_FORMAT_R1_UNORM = 385, - ISL_FORMAT_YCRCB_NORMAL = 386, - ISL_FORMAT_YCRCB_SWAPUVY = 387, - ISL_FORMAT_P2_UNORM_PALETTE0 = 388, - ISL_FORMAT_P2_UNORM_PALETTE1 = 389, - ISL_FORMAT_BC1_UNORM = 390, - ISL_FORMAT_BC2_UNORM = 391, - ISL_FORMAT_BC3_UNORM = 392, - ISL_FORMAT_BC4_UNORM = 393, - ISL_FORMAT_BC5_UNORM = 394, - ISL_FORMAT_BC1_UNORM_SRGB = 395, - ISL_FORMAT_BC2_UNORM_SRGB = 396, - ISL_FORMAT_BC3_UNORM_SRGB = 397, - ISL_FORMAT_MONO8 = 398, - ISL_FORMAT_YCRCB_SWAPUV = 399, - ISL_FORMAT_YCRCB_SWAPY = 400, - ISL_FORMAT_DXT1_RGB = 401, - ISL_FORMAT_FXT1 = 402, - ISL_FORMAT_R8G8B8_UNORM = 403, - ISL_FORMAT_R8G8B8_SNORM = 404, - ISL_FORMAT_R8G8B8_SSCALED = 405, - ISL_FORMAT_R8G8B8_USCALED = 406, - ISL_FORMAT_R64G64B64A64_FLOAT = 407, - ISL_FORMAT_R64G64B64_FLOAT = 408, - ISL_FORMAT_BC4_SNORM = 409, - ISL_FORMAT_BC5_SNORM = 410, - ISL_FORMAT_R16G16B16_FLOAT = 411, - ISL_FORMAT_R16G16B16_UNORM = 412, - ISL_FORMAT_R16G16B16_SNORM = 413, - ISL_FORMAT_R16G16B16_SSCALED = 414, - ISL_FORMAT_R16G16B16_USCALED = 415, - ISL_FORMAT_BC6H_SF16 = 417, - ISL_FORMAT_BC7_UNORM = 418, - ISL_FORMAT_BC7_UNORM_SRGB = 419, - ISL_FORMAT_BC6H_UF16 = 420, - ISL_FORMAT_PLANAR_420_8 = 421, - ISL_FORMAT_R8G8B8_UNORM_SRGB = 424, - ISL_FORMAT_ETC1_RGB8 = 425, - ISL_FORMAT_ETC2_RGB8 = 426, - ISL_FORMAT_EAC_R11 = 427, - ISL_FORMAT_EAC_RG11 = 428, - ISL_FORMAT_EAC_SIGNED_R11 = 429, - ISL_FORMAT_EAC_SIGNED_RG11 = 430, - ISL_FORMAT_ETC2_SRGB8 = 431, - ISL_FORMAT_R16G16B16_UINT = 432, - ISL_FORMAT_R16G16B16_SINT = 433, - ISL_FORMAT_R32_SFIXED = 434, - ISL_FORMAT_R10G10B10A2_SNORM = 435, - ISL_FORMAT_R10G10B10A2_USCALED = 436, - ISL_FORMAT_R10G10B10A2_SSCALED = 437, - ISL_FORMAT_R10G10B10A2_SINT = 438, - ISL_FORMAT_B10G10R10A2_SNORM = 439, - ISL_FORMAT_B10G10R10A2_USCALED = 440, - ISL_FORMAT_B10G10R10A2_SSCALED = 441, - ISL_FORMAT_B10G10R10A2_UINT = 442, - ISL_FORMAT_B10G10R10A2_SINT = 443, - ISL_FORMAT_R64G64B64A64_PASSTHRU = 444, - ISL_FORMAT_R64G64B64_PASSTHRU = 445, - ISL_FORMAT_ETC2_RGB8_PTA = 448, - ISL_FORMAT_ETC2_SRGB8_PTA = 449, - ISL_FORMAT_ETC2_EAC_RGBA8 = 450, - ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451, - ISL_FORMAT_R8G8B8_UINT = 456, - ISL_FORMAT_R8G8B8_SINT = 457, - ISL_FORMAT_RAW = 511, - - /* Hardware doesn't understand this out-of-band value */ - ISL_FORMAT_UNSUPPORTED = UINT16_MAX, -}; - -/** - * Numerical base type for channels of isl_format. - */ -enum isl_base_type { - ISL_VOID, - ISL_RAW, - ISL_UNORM, - ISL_SNORM, - ISL_UFLOAT, - ISL_SFLOAT, - ISL_UFIXED, - ISL_SFIXED, - ISL_UINT, - ISL_SINT, - ISL_USCALED, - ISL_SSCALED, -}; - -/** - * Colorspace of isl_format. - */ -enum isl_colorspace { - ISL_COLORSPACE_NONE = 0, - ISL_COLORSPACE_LINEAR, - ISL_COLORSPACE_SRGB, - ISL_COLORSPACE_YUV, -}; - -/** - * Texture compression mode of isl_format. - */ -enum isl_txc { - ISL_TXC_NONE = 0, - ISL_TXC_DXT1, - ISL_TXC_DXT3, - ISL_TXC_DXT5, - ISL_TXC_FXT1, - ISL_TXC_RGTC1, - ISL_TXC_RGTC2, - ISL_TXC_BPTC, - ISL_TXC_ETC1, - ISL_TXC_ETC2, -}; - -/** - * @brief Hardware tile mode - * - * WARNING: These values differ from the hardware enum values, which are - * unstable across hardware generations. - * - * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to - * clearly distinguish it from Yf and Ys. - */ -enum isl_tiling { - ISL_TILING_LINEAR = 0, - ISL_TILING_W, - ISL_TILING_X, - ISL_TILING_Y0, /**< Legacy Y tiling */ - ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ - ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ -}; - -/** - * @defgroup Tiling Flags - * @{ - */ -typedef uint32_t isl_tiling_flags_t; -#define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR) -#define ISL_TILING_W_BIT (1u << ISL_TILING_W) -#define ISL_TILING_X_BIT (1u << ISL_TILING_X) -#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0) -#define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf) -#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) -#define ISL_TILING_ANY_MASK (~0u) -#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) - -/** Any Y tiling, including legacy Y tiling. */ -#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \ - ISL_TILING_Yf_BIT | \ - ISL_TILING_Ys_BIT) - -/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */ -#define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \ - ISL_TILING_Ys_BIT) -/** @} */ - -/** - * @brief Logical dimension of surface. - * - * Note: There is no dimension for cube map surfaces. ISL interprets cube maps - * as 2D array surfaces. - */ -enum isl_surf_dim { - ISL_SURF_DIM_1D, - ISL_SURF_DIM_2D, - ISL_SURF_DIM_3D, -}; - -/** - * @brief Physical layout of the surface's dimensions. - */ -enum isl_dim_layout { - /** - * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section - * 6.17.3: 2D Surfaces. - * - * On many gens, 1D surfaces share the same layout as 2D surfaces. From - * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces: - * - * One-dimensional surfaces are identical to 2D surfaces with height of - * one. - * - * @invariant isl_surf::phys_level0_sa::depth == 1 - */ - ISL_DIM_LAYOUT_GEN4_2D, - - /** - * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section - * 6.17.5: 3D Surfaces. - * - * @invariant isl_surf::phys_level0_sa::array_len == 1 - */ - ISL_DIM_LAYOUT_GEN4_3D, - - /** - * For details, see the Skylake BSpec >> Memory Views >> Common Surface - * Formats >> Surface Layout and Tiling >> » 1D Surfaces. - */ - ISL_DIM_LAYOUT_GEN9_1D, -}; - -/* TODO(chadv): Explain */ -enum isl_array_pitch_span { - ISL_ARRAY_PITCH_SPAN_FULL, - ISL_ARRAY_PITCH_SPAN_COMPACT, -}; - -/** - * @defgroup Surface Usage - * @{ - */ -typedef uint64_t isl_surf_usage_flags_t; -#define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0) -#define ISL_SURF_USAGE_DEPTH_BIT (1u << 1) -#define ISL_SURF_USAGE_STENCIL_BIT (1u << 2) -#define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3) -#define ISL_SURF_USAGE_CUBE_BIT (1u << 4) -#define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5) -#define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6) -#define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7) -#define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8) -#define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9) -#define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10) -#define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11) -/** @} */ - -/** - * Identical to VkSampleCountFlagBits. - */ -enum isl_sample_count { - ISL_SAMPLE_COUNT_1_BIT = 1u, - ISL_SAMPLE_COUNT_2_BIT = 2u, - ISL_SAMPLE_COUNT_4_BIT = 4u, - ISL_SAMPLE_COUNT_8_BIT = 8u, - ISL_SAMPLE_COUNT_16_BIT = 16u, -}; -typedef uint32_t isl_sample_count_mask_t; - -/** - * @brief Multisample Format - */ -enum isl_msaa_layout { - /** - * @brief Suface is single-sampled. - */ - ISL_MSAA_LAYOUT_NONE, - - /** - * @brief [SNB+] Interleaved Multisample Format - * - * In this format, multiple samples are interleaved into each cacheline. - * In other words, the sample index is swizzled into the low 6 bits of the - * surface's virtual address space. - * - * For example, suppose the surface is legacy Y tiled, is 4x multisampled, - * and its pixel format is 32bpp. Then the first cacheline is arranged - * thus: - * - * (0,0,0) (0,1,0) (0,0,1) (1,0,1) - * (1,0,0) (1,1,0) (0,1,1) (1,1,1) - * - * (0,0,2) (1,0,2) (0,0,3) (1,0,3) - * (0,1,2) (1,1,2) (0,1,3) (1,1,3) - * - * The hardware docs refer to this format with multiple terms. In - * Sandybridge, this is the only multisample format; so no term is used. - * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved - * Multisample Surface). Later hardware docs additionally refer to this - * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for - * color surfaces). - * - * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled - * Surface Behavior". - * - * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved - * Multisampled Surfaces". - */ - ISL_MSAA_LAYOUT_INTERLEAVED, - - /** - * @brief [IVB+] Array Multisample Format - * - * In this format, the surface's physical layout resembles that of a - * 2D array surface. - * - * Suppose the multisample surface's logical extent is (w, h) and its - * sample count is N. Then surface's physical extent is the same as - * a singlesample 2D surface whose logical extent is (w, h) and array - * length is N. Array slice `i` contains the pixel values for sample - * index `i`. - * - * The Ivybridge docs refer to surfaces in this format as UMS - * (Uncompressed Multsample Layout) and CMS (Compressed Multisample - * Surface). The Broadwell docs additionally refer to this format as - * MSFMT_MSS (MSS=Multisample Surface Storage). - * - * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed - * Multisample Surfaces". - * - * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed - * Multisample Surfaces". - */ - ISL_MSAA_LAYOUT_ARRAY, -}; - - -struct isl_device { - const struct brw_device_info *info; - bool use_separate_stencil; - bool has_bit6_swizzling; -}; - -struct isl_extent2d { - union { uint32_t w, width; }; - union { uint32_t h, height; }; -}; - -struct isl_extent3d { - union { uint32_t w, width; }; - union { uint32_t h, height; }; - union { uint32_t d, depth; }; -}; - -struct isl_extent4d { - union { uint32_t w, width; }; - union { uint32_t h, height; }; - union { uint32_t d, depth; }; - union { uint32_t a, array_len; }; -}; - -struct isl_channel_layout { - enum isl_base_type type; - uint8_t bits; /**< Size in bits */ -}; - -/** - * Each format has 3D block extent (width, height, depth). The block extent of - * compressed formats is that of the format's compression block. For example, - * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block - * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is - * is (w=1, h=1, d=1). - */ -struct isl_format_layout { - enum isl_format format; - - uint8_t bs; /**< Block size, in bytes, rounded towards 0 */ - uint8_t bw; /**< Block width, in pixels */ - uint8_t bh; /**< Block height, in pixels */ - uint8_t bd; /**< Block depth, in pixels */ - - struct { - struct isl_channel_layout r; /**< Red channel */ - struct isl_channel_layout g; /**< Green channel */ - struct isl_channel_layout b; /**< Blue channel */ - struct isl_channel_layout a; /**< Alpha channel */ - struct isl_channel_layout l; /**< Luminance channel */ - struct isl_channel_layout i; /**< Intensity channel */ - struct isl_channel_layout p; /**< Palette channel */ - } channels; - - enum isl_colorspace colorspace; - enum isl_txc txc; -}; - -struct isl_tile_info { - enum isl_tiling tiling; - uint32_t width; /**< in bytes */ - uint32_t height; /**< in rows of memory */ - uint32_t size; /**< in bytes */ -}; - -/** - * @brief Input to surface initialization - * - * @invariant width >= 1 - * @invariant height >= 1 - * @invariant depth >= 1 - * @invariant levels >= 1 - * @invariant samples >= 1 - * @invariant array_len >= 1 - * - * @invariant if 1D then height == 1 and depth == 1 and samples == 1 - * @invariant if 2D then depth == 1 - * @invariant if 3D then array_len == 1 and samples == 1 - */ -struct isl_surf_init_info { - enum isl_surf_dim dim; - enum isl_format format; - - uint32_t width; - uint32_t height; - uint32_t depth; - uint32_t levels; - uint32_t array_len; - uint32_t samples; - - /** Lower bound for isl_surf::alignment, in bytes. */ - uint32_t min_alignment; - - /** Lower bound for isl_surf::pitch, in bytes. */ - uint32_t min_pitch; - - isl_surf_usage_flags_t usage; - - /** Flags that alter how ISL selects isl_surf::tiling. */ - isl_tiling_flags_t tiling_flags; -}; - -struct isl_surf { - enum isl_surf_dim dim; - enum isl_dim_layout dim_layout; - enum isl_msaa_layout msaa_layout; - enum isl_tiling tiling; - enum isl_format format; - - /** - * Alignment of the upper-left sample of each subimage, in units of surface - * elements. - */ - struct isl_extent3d image_alignment_el; - - /** - * Logical extent of the surface's base level, in units of pixels. This is - * identical to the extent defined in isl_surf_init_info. - */ - struct isl_extent4d logical_level0_px; - - /** - * Physical extent of the surface's base level, in units of physical - * surface samples and aligned to the format's compression block. - * - * Consider isl_dim_layout as an operator that transforms a logical surface - * layout to a physical surface layout. Then - * - * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px) - * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout - */ - struct isl_extent4d phys_level0_sa; - - uint32_t levels; - uint32_t samples; - - /** Total size of the surface, in bytes. */ - uint32_t size; - - /** Required alignment for the surface's base address. */ - uint32_t alignment; - - /** - * Pitch between vertically adjacent surface elements, in bytes. - */ - uint32_t row_pitch; - - /** - * Pitch between physical array slices, in rows of surface elements. - */ - uint32_t array_pitch_el_rows; - - enum isl_array_pitch_span array_pitch_span; - - /** Copy of isl_surf_init_info::usage. */ - isl_surf_usage_flags_t usage; -}; - -extern const struct isl_format_layout isl_format_layouts[]; - -void -isl_device_init(struct isl_device *dev, - const struct brw_device_info *info, - bool has_bit6_swizzling); - -isl_sample_count_mask_t ATTRIBUTE_CONST -isl_device_get_sample_counts(struct isl_device *dev); - -static inline const struct isl_format_layout * ATTRIBUTE_CONST -isl_format_get_layout(enum isl_format fmt) -{ - return &isl_format_layouts[fmt]; -} - -bool -isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST; - -static inline bool -isl_format_is_compressed(enum isl_format fmt) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - return fmtl->txc != ISL_TXC_NONE; -} - -static inline bool -isl_format_has_bc_compression(enum isl_format fmt) -{ - switch (isl_format_get_layout(fmt)->txc) { - case ISL_TXC_DXT1: - case ISL_TXC_DXT3: - case ISL_TXC_DXT5: - return true; - case ISL_TXC_NONE: - case ISL_TXC_FXT1: - case ISL_TXC_RGTC1: - case ISL_TXC_RGTC2: - case ISL_TXC_BPTC: - case ISL_TXC_ETC1: - case ISL_TXC_ETC2: - return false; - } - - unreachable("bad texture compression mode"); - return false; -} - -static inline bool -isl_format_is_yuv(enum isl_format fmt) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - return fmtl->colorspace == ISL_COLORSPACE_YUV; -} - -static inline bool -isl_format_block_is_1x1x1(enum isl_format fmt) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1; -} - -static inline bool -isl_format_is_rgb(enum isl_format fmt) -{ - return isl_format_layouts[fmt].channels.r.bits > 0 && - isl_format_layouts[fmt].channels.g.bits > 0 && - isl_format_layouts[fmt].channels.b.bits > 0 && - isl_format_layouts[fmt].channels.a.bits == 0; -} - -enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; -enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST; - -bool isl_is_storage_image_format(enum isl_format fmt); - -enum isl_format -isl_lower_storage_image_format(const struct isl_device *dev, - enum isl_format fmt); - -static inline bool -isl_tiling_is_any_y(enum isl_tiling tiling) -{ - return (1u << tiling) & ISL_TILING_ANY_MASK; -} - -static inline bool -isl_tiling_is_std_y(enum isl_tiling tiling) -{ - return (1u << tiling) & ISL_TILING_STD_Y_MASK; -} - -bool -isl_tiling_get_info(const struct isl_device *dev, - enum isl_tiling tiling, - uint32_t format_block_size, - struct isl_tile_info *info); - -void -isl_tiling_get_extent(const struct isl_device *dev, - enum isl_tiling tiling, - uint32_t format_block_size, - struct isl_extent2d *e); -bool -isl_surf_choose_tiling(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling *tiling); - -static inline bool -isl_surf_usage_is_display(isl_surf_usage_flags_t usage) -{ - return usage & ISL_SURF_USAGE_DISPLAY_BIT; -} - -static inline bool -isl_surf_usage_is_depth(isl_surf_usage_flags_t usage) -{ - return usage & ISL_SURF_USAGE_DEPTH_BIT; -} - -static inline bool -isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage) -{ - return usage & ISL_SURF_USAGE_STENCIL_BIT; -} - -static inline bool -isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage) -{ - return (usage & ISL_SURF_USAGE_DEPTH_BIT) && - (usage & ISL_SURF_USAGE_STENCIL_BIT); -} - -static inline bool -isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage) -{ - return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT); -} - -static inline bool -isl_surf_info_is_z16(const struct isl_surf_init_info *info) -{ - return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && - (info->format == ISL_FORMAT_R16_UNORM); -} - -static inline bool -isl_surf_info_is_z32_float(const struct isl_surf_init_info *info) -{ - return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && - (info->format == ISL_FORMAT_R32_FLOAT); -} - -static inline struct isl_extent2d -isl_extent2d(uint32_t width, uint32_t height) -{ - return (struct isl_extent2d) { .w = width, .h = height }; -} - -static inline struct isl_extent3d -isl_extent3d(uint32_t width, uint32_t height, uint32_t depth) -{ - return (struct isl_extent3d) { .w = width, .h = height, .d = depth }; -} - -static inline struct isl_extent4d -isl_extent4d(uint32_t width, uint32_t height, uint32_t depth, - uint32_t array_len) -{ - return (struct isl_extent4d) { - .w = width, - .h = height, - .d = depth, - .a = array_len, - }; -} - -#define isl_surf_init(dev, surf, ...) \ - isl_surf_init_s((dev), (surf), \ - &(struct isl_surf_init_info) { __VA_ARGS__ }); - -bool -isl_surf_init_s(const struct isl_device *dev, - struct isl_surf *surf, - const struct isl_surf_init_info *restrict info); - -void -isl_surf_get_tile_info(const struct isl_device *dev, - const struct isl_surf *surf, - struct isl_tile_info *tile_info); - -/** - * Alignment of the upper-left sample of each subimage, in units of surface - * elements. - */ -static inline struct isl_extent3d -isl_surf_get_image_alignment_el(const struct isl_surf *surf) -{ - return surf->image_alignment_el; -} - -/** - * Alignment of the upper-left sample of each subimage, in units of surface - * samples. - */ -static inline struct isl_extent3d -isl_surf_get_image_alignment_sa(const struct isl_surf *surf) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - - return (struct isl_extent3d) { - .w = fmtl->bw * surf->image_alignment_el.w, - .h = fmtl->bh * surf->image_alignment_el.h, - .d = fmtl->bd * surf->image_alignment_el.d, - }; -} - -/** - * Pitch between vertically adjacent surface elements, in bytes. - */ -static inline uint32_t -isl_surf_get_row_pitch(const struct isl_surf *surf) -{ - return surf->row_pitch; -} - -/** - * Pitch between vertically adjacent surface elements, in units of surface elements. - */ -static inline uint32_t -isl_surf_get_row_pitch_el(const struct isl_surf *surf) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - - assert(surf->row_pitch % fmtl->bs == 0); - return surf->row_pitch / fmtl->bs; -} - -/** - * Pitch between physical array slices, in rows of surface elements. - */ -static inline uint32_t -isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf) -{ - return surf->array_pitch_el_rows; -} - -/** - * Pitch between physical array slices, in units of surface elements. - */ -static inline uint32_t -isl_surf_get_array_pitch_el(const struct isl_surf *surf) -{ - return isl_surf_get_array_pitch_el_rows(surf) * - isl_surf_get_row_pitch_el(surf); -} - -/** - * Pitch between physical array slices, in rows of surface samples. - */ -static inline uint32_t -isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf); -} - -/** - * Pitch between physical array slices, in bytes. - */ -static inline uint32_t -isl_surf_get_array_pitch(const struct isl_surf *surf) -{ - return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; -} - -/** - * Calculate the offset, in units of surface elements, to a subimage in the - * surface. - * - * @invariant level < surface levels - * @invariant logical_array_layer < logical array length of surface - * @invariant logical_z_offset_px < logical depth of surface at level - */ -void -isl_surf_get_image_offset_el(const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset_px, - uint32_t *x_offset_el, - uint32_t *y_offset_el); - -/** - * @brief Calculate the intratile offsets to a subimage in the surface. - * - * In @a base_address_offset return the offset from the base of the surface to - * the base address of the first tile of the subimage. In @a x_offset_el and - * @a y_offset_el, return the offset, in units of surface elements, from the - * tile's base to the subimage's first surface element. The x and y offsets - * are intratile offsets; that is, they do not exceed the boundary of the - * surface's tiling format. - */ -void -isl_surf_get_image_intratile_offset_el(const struct isl_device *dev, - const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset, - uint32_t *base_address_offset, - uint32_t *x_offset_el, - uint32_t *y_offset_el); - -/** - * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat - * - * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT - * @pre surf->format must be a valid format for depth surfaces - */ -uint32_t -isl_surf_get_depth_format(const struct isl_device *dev, - const struct isl_surf *surf); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_format.c b/src/isl/isl_format.c deleted file mode 100644 index 0fe6e9b83ab..00000000000 --- a/src/isl/isl_format.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include - -#include "isl.h" - -bool -isl_format_has_sint_channel(enum isl_format fmt) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - return fmtl->channels.r.type == ISL_SINT || - fmtl->channels.g.type == ISL_SINT || - fmtl->channels.b.type == ISL_SINT || - fmtl->channels.a.type == ISL_SINT || - fmtl->channels.l.type == ISL_SINT || - fmtl->channels.i.type == ISL_SINT || - fmtl->channels.p.type == ISL_SINT || - fmtl->channels.g.type == ISL_SINT; -} - -enum isl_format -isl_format_rgb_to_rgba(enum isl_format rgb) -{ - assert(isl_format_is_rgb(rgb)); - - switch (rgb) { - case ISL_FORMAT_R32G32B32_FLOAT: return ISL_FORMAT_R32G32B32A32_FLOAT; - case ISL_FORMAT_R32G32B32_SINT: return ISL_FORMAT_R32G32B32A32_SINT; - case ISL_FORMAT_R32G32B32_UINT: return ISL_FORMAT_R32G32B32A32_UINT; - case ISL_FORMAT_R32G32B32_UNORM: return ISL_FORMAT_R32G32B32A32_UNORM; - case ISL_FORMAT_R32G32B32_SNORM: return ISL_FORMAT_R32G32B32A32_SNORM; - case ISL_FORMAT_R32G32B32_SSCALED: return ISL_FORMAT_R32G32B32A32_SSCALED; - case ISL_FORMAT_R32G32B32_USCALED: return ISL_FORMAT_R32G32B32A32_USCALED; - case ISL_FORMAT_R32G32B32_SFIXED: return ISL_FORMAT_R32G32B32A32_SFIXED; - case ISL_FORMAT_R8G8B8_UNORM: return ISL_FORMAT_R8G8B8A8_UNORM; - case ISL_FORMAT_R8G8B8_SNORM: return ISL_FORMAT_R8G8B8A8_SNORM; - case ISL_FORMAT_R8G8B8_SSCALED: return ISL_FORMAT_R8G8B8A8_SSCALED; - case ISL_FORMAT_R8G8B8_USCALED: return ISL_FORMAT_R8G8B8A8_USCALED; - case ISL_FORMAT_R16G16B16_FLOAT: return ISL_FORMAT_R16G16B16A16_FLOAT; - case ISL_FORMAT_R16G16B16_UNORM: return ISL_FORMAT_R16G16B16A16_UNORM; - case ISL_FORMAT_R16G16B16_SNORM: return ISL_FORMAT_R16G16B16A16_SNORM; - case ISL_FORMAT_R16G16B16_SSCALED: return ISL_FORMAT_R16G16B16A16_SSCALED; - case ISL_FORMAT_R16G16B16_USCALED: return ISL_FORMAT_R16G16B16A16_USCALED; - case ISL_FORMAT_R8G8B8_UNORM_SRGB: return ISL_FORMAT_R8G8B8A8_UNORM_SRGB; - case ISL_FORMAT_R16G16B16_UINT: return ISL_FORMAT_R16G16B16A16_UINT; - case ISL_FORMAT_R16G16B16_SINT: return ISL_FORMAT_R16G16B16A16_SINT; - case ISL_FORMAT_R8G8B8_UINT: return ISL_FORMAT_R8G8B8A8_UINT; - case ISL_FORMAT_R8G8B8_SINT: return ISL_FORMAT_R8G8B8A8_SINT; - default: - return ISL_FORMAT_UNSUPPORTED; - } -} - -enum isl_format -isl_format_rgb_to_rgbx(enum isl_format rgb) -{ - assert(isl_format_is_rgb(rgb)); - - switch (rgb) { - case ISL_FORMAT_R32G32B32_FLOAT: - return ISL_FORMAT_R32G32B32X32_FLOAT; - case ISL_FORMAT_R16G16B16_UNORM: - return ISL_FORMAT_R16G16B16X16_UNORM; - case ISL_FORMAT_R16G16B16_FLOAT: - return ISL_FORMAT_R16G16B16X16_FLOAT; - case ISL_FORMAT_R8G8B8_UNORM: - return ISL_FORMAT_R8G8B8X8_UNORM; - case ISL_FORMAT_R8G8B8_UNORM_SRGB: - return ISL_FORMAT_R8G8B8X8_UNORM_SRGB; - default: - return ISL_FORMAT_UNSUPPORTED; - } -} diff --git a/src/isl/isl_format_layout.csv b/src/isl/isl_format_layout.csv deleted file mode 100644 index af2786ae630..00000000000 --- a/src/isl/isl_format_layout.csv +++ /dev/null @@ -1,287 +0,0 @@ -# Copyright 2015 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. - -# -# @file -# @brief Layout of all hardware surface formats -# -# For the official list, see Broadwell PRM: Volume 2b: Command Reference: -# Enumerations: SURFACE_FORMAT. -# - - -# Columns: -# name: format name in PRM -# bpb: bits per block -# bw: block width, in pixels -# bh: block height, in pixels -# bd: block depth, in pixels -# r: red channel, data type and bitwidth -# g: green channel -# b: blue channel -# a: alpha channel -# l: luminance channel -# i: intensity channel -# p: palette channel -# space: colorspace -# txc: texture compression -# -# Data Types: -# x: void -# r: raw -# un: unorm -# sn: snorm -# uf: ufloat -# sf: sfloat -# ux: ufixed -# sx: sfixed -# ui: uint -# si: sint -# us: uscaled -# ss: sscaled - - -# Table is aligned with the Vim commands below, using the Align plugin: -# :AlignCtrl lr+ p8000000000000P1 -# /^# name/,$ Align, - -# name , bpb, bw, bh, bd, r, g, b, a, l, i, p, space, txc -R32G32B32A32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, sf32, , , , linear, -R32G32B32A32_SINT , 128, 1, 1, 1, si32, si32, si32, si32, , , , linear, -R32G32B32A32_UINT , 128, 1, 1, 1, ui32, ui32, ui32, ui32, , , , linear, -R32G32B32A32_UNORM , 128, 1, 1, 1, un32, un32, un32, un32, , , , linear, -R32G32B32A32_SNORM , 128, 1, 1, 1, sn32, sn32, sn32, sn32, , , , linear, -R64G64_FLOAT , 128, 1, 1, 1, sf64, sf64, , , , , , linear, -R32G32B32X32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, x32, , , , linear, -R32G32B32A32_SSCALED , 128, 1, 1, 1, ss32, ss32, ss32, ss32, , , , linear, -R32G32B32A32_USCALED , 128, 1, 1, 1, us32, us32, us32, us32, , , , linear, -R32G32B32A32_SFIXED , 128, 1, 1, 1, sx32, sx32, sx32, sx32, , , , linear, -R64G64_PASSTHRU , 128, 1, 1, 1, r64, r64, , , , , , , -R32G32B32_FLOAT , 96, 1, 1, 1, sf32, sf32, sf32, , , , , linear, -R32G32B32_SINT , 96, 1, 1, 1, si32, si32, si32, , , , , linear, -R32G32B32_UINT , 96, 1, 1, 1, ui32, ui32, ui32, , , , , linear, -R32G32B32_UNORM , 96, 1, 1, 1, un32, un32, un32, , , , , linear, -R32G32B32_SNORM , 96, 1, 1, 1, sn32, sn32, sn32, , , , , linear, -R32G32B32_SSCALED , 96, 1, 1, 1, ss32, ss32, ss32, , , , , linear, -R32G32B32_USCALED , 96, 1, 1, 1, us32, us32, us32, , , , , linear, -R32G32B32_SFIXED , 96, 1, 1, 1, sx32, sx32, sx32, , , , , linear, -R16G16B16A16_UNORM , 64, 1, 1, 1, un16, un16, un16, un16, , , , linear, -R16G16B16A16_SNORM , 64, 1, 1, 1, sn16, sn16, sn16, sn16, , , , linear, -R16G16B16A16_SINT , 64, 1, 1, 1, si16, si16, si16, si16, , , , linear, -R16G16B16A16_UINT , 64, 1, 1, 1, ui16, ui16, ui16, ui16, , , , linear, -R16G16B16A16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, sf16, , , , linear, -R32G32_FLOAT , 64, 1, 1, 1, sf32, sf32, , , , , , linear, -R32G32_SINT , 64, 1, 1, 1, si32, si32, , , , , , linear, -R32G32_UINT , 64, 1, 1, 1, ui32, ui32, , , , , , linear, -R32_FLOAT_X8X24_TYPELESS , 64, 1, 1, 1, sf32, x8, x24, , , , , linear, -X32_TYPELESS_G8X24_UINT , 64, 1, 1, 1, x32, ui8, x24, , , , , linear, -L32A32_FLOAT , 64, 1, 1, 1, , , , sf32, sf32, , , linear, -R32G32_UNORM , 64, 1, 1, 1, un32, un32, , , , , , linear, -R32G32_SNORM , 64, 1, 1, 1, sn32, sn32, , , , , , linear, -R64_FLOAT , 64, 1, 1, 1, sf64, , , , , , , linear, -R16G16B16X16_UNORM , 64, 1, 1, 1, un16, un16, un16, x16, , , , linear, -R16G16B16X16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, x16, , , , linear, -A32X32_FLOAT , 64, 1, 1, 1, , , , sf32, x32, , , alpha, -L32X32_FLOAT , 64, 1, 1, 1, , , , x32, sf32, , , linear, -I32X32_FLOAT , 64, 1, 1, 1, , , , x32, , sf32, , linear, -R16G16B16A16_SSCALED , 64, 1, 1, 1, ss16, ss16, ss16, ss16, , , , linear, -R16G16B16A16_USCALED , 64, 1, 1, 1, us16, us16, us16, us16, , , , linear, -R32G32_SSCALED , 64, 1, 1, 1, ss32, ss32, , , , , , linear, -R32G32_USCALED , 64, 1, 1, 1, us32, us32, , , , , , linear, -R32G32_SFIXED , 64, 1, 1, 1, sx32, sx32, , , , , , linear, -R64_PASSTHRU , 64, 1, 1, 1, r64, , , , , , , , -B8G8R8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, -B8G8R8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, -R10G10B10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, -R10G10B10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, -R10G10B10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, -R10G10B10_SNORM_A2_UNORM , 32, 1, 1, 1, sn10, sn10, sn10, un2, , , , linear, -R8G8B8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, -R8G8B8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, -R8G8B8A8_SNORM , 32, 1, 1, 1, sn8, sn8, sn8, sn8, , , , linear, -R8G8B8A8_SINT , 32, 1, 1, 1, si8, si8, si8, si8, , , , linear, -R8G8B8A8_UINT , 32, 1, 1, 1, ui8, ui8, ui8, ui8, , , , linear, -R16G16_UNORM , 32, 1, 1, 1, un16, un16, , , , , , linear, -R16G16_SNORM , 32, 1, 1, 1, sn16, sn16, , , , , , linear, -R16G16_SINT , 32, 1, 1, 1, si16, si16, , , , , , linear, -R16G16_UINT , 32, 1, 1, 1, ui16, ui16, , , , , , linear, -R16G16_FLOAT , 32, 1, 1, 1, sf16, sf16, , , , , , linear, -B10G10R10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, -B10G10R10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, -R11G11B10_FLOAT , 32, 1, 1, 1, uf11, uf11, uf10, , , , , linear, -R32_SINT , 32, 1, 1, 1, si32, , , , , , , linear, -R32_UINT , 32, 1, 1, 1, ui32, , , , , , , linear, -R32_FLOAT , 32, 1, 1, 1, sf32, , , , , , , linear, -R24_UNORM_X8_TYPELESS , 32, 1, 1, 1, un24, x8, , , , , , linear, -X24_TYPELESS_G8_UINT , 32, 1, 1, 1, x24, ui8, , , , , , linear, -L32_UNORM , 32, 1, 1, 1, , , , , un32, , , linear, -A32_UNORM , 32, 1, 1, 1, , , , un32, , , , alpha, -L16A16_UNORM , 32, 1, 1, 1, , , , un16, un16, , , linear, -I24X8_UNORM , 32, 1, 1, 1, , , , x8, , un24, , linear, -L24X8_UNORM , 32, 1, 1, 1, , , , x8, un24, , , linear, -A24X8_UNORM , 32, 1, 1, 1, , , , un24, x8, , , alpha, -I32_FLOAT , 32, 1, 1, 1, , , , , , sf32, , linear, -L32_FLOAT , 32, 1, 1, 1, , , , , sf32, , , linear, -A32_FLOAT , 32, 1, 1, 1, , , , sf32, , , , alpha, -X8B8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, -A8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, x8, un8, , , , linear, -B8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, -B8G8R8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, -B8G8R8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, -R8G8B8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, -R8G8B8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, -R9G9B9E5_SHAREDEXP , 32, 1, 1, 1, ui9, ui9, ui9, , , , , linear, -B10G10R10X2_UNORM , 32, 1, 1, 1, un10, un10, un10, x2, , , , linear, -L16A16_FLOAT , 32, 1, 1, 1, , , , sf16, sf16, , , linear, -R32_UNORM , 32, 1, 1, 1, un32, , , , , , , linear, -R32_SNORM , 32, 1, 1, 1, sn32, , , , , , , linear, -R10G10B10X2_USCALED , 32, 1, 1, 1, us10, us10, us10, x2, , , , linear, -R8G8B8A8_SSCALED , 32, 1, 1, 1, ss8, ss8, ss8, ss8, , , , linear, -R8G8B8A8_USCALED , 32, 1, 1, 1, us8, us8, us8, us8, , , , linear, -R16G16_SSCALED , 32, 1, 1, 1, ss16, ss6, , , , , , linear, -R16G16_USCALED , 32, 1, 1, 1, us16, us16, , , , , , linear, -R32_SSCALED , 32, 1, 1, 1, ss32, , , , , , , linear, -R32_USCALED , 32, 1, 1, 1, us32, , , , , , , linear, -B5G6R5_UNORM , 16, 1, 1, 1, un5, un6, un5, , , , , linear, -B5G6R5_UNORM_SRGB , 16, 1, 1, 1, un5, un6, un5, , , , , srgb, -B5G5R5A1_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, -B5G5R5A1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, un1, , , , srgb, -B4G4R4A4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, -B4G4R4A4_UNORM_SRGB , 16, 1, 1, 1, un4, un4, un4, un4, , , , srgb, -R8G8_UNORM , 16, 1, 1, 1, un8, un8, , , , , , linear, -R8G8_SNORM , 16, 1, 1, 1, sn8, sn8, , , , , , linear, -R8G8_SINT , 16, 1, 1, 1, si8, si8, , , , , , linear, -R8G8_UINT , 16, 1, 1, 1, ui8, ui8, , , , , , linear, -R16_UNORM , 16, 1, 1, 1, un16, , , , , , , linear, -R16_SNORM , 16, 1, 1, 1, sn16, , , , , , , linear, -R16_SINT , 16, 1, 1, 1, si16, , , , , , , linear, -R16_UINT , 16, 1, 1, 1, ui16, , , , , , , linear, -R16_FLOAT , 16, 1, 1, 1, sf16, , , , , , , linear, -A8P8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, -A8P8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, -I16_UNORM , 16, 1, 1, 1, , , , , , un16, , linear, -L16_UNORM , 16, 1, 1, 1, , , , , un16, , , linear, -A16_UNORM , 16, 1, 1, 1, , , , un16, , , , alpha, -L8A8_UNORM , 16, 1, 1, 1, , , , un8, un8, , , linear, -I16_FLOAT , 16, 1, 1, 1, , , , , , sf16, , linear, -L16_FLOAT , 16, 1, 1, 1, , , , , sf16, , , linear, -A16_FLOAT , 16, 1, 1, 1, , , , sf16, , , , alpha, -L8A8_UNORM_SRGB , 16, 1, 1, 1, , , , un8, un8, , , srgb, -R5G5_SNORM_B6_UNORM , 16, 1, 1, 1, sn5, sn5, un6, , , , , linear, -B5G5R5X1_UNORM , 16, 1, 1, 1, un5, un5, un5, x1, , , , linear, -B5G5R5X1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, x1, , , , srgb, -R8G8_SSCALED , 16, 1, 1, 1, ss8, ss8, , , , , , linear, -R8G8_USCALED , 16, 1, 1, 1, us8, us8, , , , , , linear, -R16_SSCALED , 16, 1, 1, 1, ss16, , , , , , , linear, -R16_USCALED , 16, 1, 1, 1, us16, , , , , , , linear, -P8A8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, -P8A8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, -A1B5G5R5_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, -A4B4G4R4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, -L8A8_UINT , 16, 1, 1, 1, , , , ui8, ui8, , , linear, -L8A8_SINT , 16, 1, 1, 1, , , , si8, si8, , , linear, -R8_UNORM , 8, 1, 1, 1, un8, , , , , , , linear, -R8_SNORM , 8, 1, 1, 1, sn8, , , , , , , linear, -R8_SINT , 8, 1, 1, 1, si8, , , , , , , linear, -R8_UINT , 8, 1, 1, 1, ui8, , , , , , , linear, -A8_UNORM , 8, 1, 1, 1, , , , un8, , , , alpha, -I8_UNORM , 8, 1, 1, 1, , , , , , un8, , linear, -L8_UNORM , 8, 1, 1, 1, , , , , un8, , , linear, -P4A4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, -A4P4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, -R8_SSCALED , 8, 1, 1, 1, ss8, , , , , , , linear, -R8_USCALED , 8, 1, 1, 1, us8, , , , , , , linear, -P8_UNORM_PALETTE0 , 8, 1, 1, 1, , , , , , , un8, linear, -L8_UNORM_SRGB , 8, 1, 1, 1, , , , , un8, , , linear, -P8_UNORM_PALETTE1 , 8, 1, 1, 1, , , , , , , un8, linear, -P4A4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, -A4P4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, -Y8_UNORM , 0, 0, 0, 0, , , , , , , , yuv, -L8_UINT , 8, 1, 1, 1, , , , , ui8, , , linear, -L8_SINT , 8, 1, 1, 1, , , , , si8, , , linear, -I8_UINT , 8, 1, 1, 1, , , , , , ui8, , linear, -I8_SINT , 8, 1, 1, 1, , , , , , si8, , linear, -DXT1_RGB_SRGB , 64, 4, 4, 1, un4, un4, un4, , , , , srgb, dxt1 -R1_UNORM , 1, 1, 1, 1, un1, , , , , , , linear, -YCRCB_NORMAL , 0, 0, 0, 0, , , , , , , , yuv, -YCRCB_SWAPUVY , 0, 0, 0, 0, , , , , , , , yuv, -P2_UNORM_PALETTE0 , 2, 1, 1, 1, , , , , , , un2, linear, -P2_UNORM_PALETTE1 , 2, 1, 1, 1, , , , , , , un2, linear, -BC1_UNORM , 64, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt1 -BC2_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt3 -BC3_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt5 -BC4_UNORM , 64, 4, 4, 1, un8, , , , , , , linear, rgtc1 -BC5_UNORM , 128, 4, 4, 1, un8, un8, , , , , , linear, rgtc2 -BC1_UNORM_SRGB , 64, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt1 -BC2_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt3 -BC3_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt5 -MONO8 , 1, 1, 1, 1, , , , , , , , , -YCRCB_SWAPUV , 0, 0, 0, 0, , , , , , , , yuv, -YCRCB_SWAPY , 0, 0, 0, 0, , , , , , , , yuv, -DXT1_RGB , 64, 4, 4, 1, un4, un4, un4, , , , , linear, dxt1 -FXT1 , 128, 8, 4, 1, un4, un4, un4, , , , , linear, fxt1 -R8G8B8_UNORM , 24, 1, 1, 1, un8, un8, un8, , , , , linear, -R8G8B8_SNORM , 24, 1, 1, 1, sn8, sn8, sn8, , , , , linear, -R8G8B8_SSCALED , 24, 1, 1, 1, ss8, ss8, ss8, , , , , linear, -R8G8B8_USCALED , 24, 1, 1, 1, us8, us8, us8, , , , , linear, -R64G64B64A64_FLOAT , 256, 1, 1, 1, sf64, sf64, sf64, sf64, , , , linear, -R64G64B64_FLOAT , 196, 1, 1, 1, sf64, sf64, sf64, , , , , linear, -BC4_SNORM , 64, 4, 4, 1, sn8, , , , , , , linear, rgtc1 -BC5_SNORM , 128, 4, 4, 1, sn8, sn8, , , , , , linear, rgtc2 -R16G16B16_FLOAT , 48, 1, 1, 1, sf16, sf16, sf16, , , , , linear, -R16G16B16_UNORM , 48, 1, 1, 1, un16, un16, un16, , , , , linear, -R16G16B16_SNORM , 48, 1, 1, 1, sn16, sn16, sn16, , , , , linear, -R16G16B16_SSCALED , 48, 1, 1, 1, ss16, ss16, ss16, , , , , linear, -R16G16B16_USCALED , 48, 1, 1, 1, us16, us16, us16, , , , , linear, -BC6H_SF16 , 128, 4, 4, 1, sf16, sf16, sf16, , , , , linear, bptc -BC7_UNORM , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, bptc -BC7_UNORM_SRGB , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, bptc -BC6H_UF16 , 128, 4, 4, 1, uf16, uf16, uf16, , , , , linear, bptc -PLANAR_420_8 , 0, 0, 0, 0, , , , , , , , yuv, -R8G8B8_UNORM_SRGB , 24, 1, 1, 1, un8, un8, un8, , , , , srgb, -ETC1_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc1 -ETC2_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc2 -EAC_R11 , 64, 4, 4, 1, un11, , , , , , , linear, etc2 -EAC_RG11 , 128, 4, 4, 1, un11, un11, , , , , , linear, etc2 -EAC_SIGNED_R11 , 64, 4, 4, 1, sn11, , , , , , , linear, etc2 -EAC_SIGNED_RG11 , 128, 4, 4, 1, sn11, sn11, , , , , , linear, etc2 -ETC2_SRGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , srgb, etc2 -R16G16B16_UINT , 48, 1, 1, 1, ui16, ui16, ui16, , , , , linear, -R16G16B16_SINT , 48, 1, 1, 1, si16, si16, si16, , , , , linear, -R32_SFIXED , 32, 1, 1, 1, sx16, , , , , , , linear, -R10G10B10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, -R10G10B10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, -R10G10B10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, -R10G10B10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, -B10G10R10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, -B10G10R10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, -B10G10R10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, -B10G10R10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, -B10G10R10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, -R64G64B64A64_PASSTHRU , 256, 1, 1, 1, r64, r64, r64, r64, , , , , -R64G64B64_PASSTHRU , 192, 1, 1, 1, r64, r64, r64, , , , , , -ETC2_RGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , linear, etc2 -ETC2_SRGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , srgb, etc2 -ETC2_EAC_RGBA8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, etc2 -ETC2_EAC_SRGB8_A8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, etc2 -R8G8B8_UINT , 24, 1, 1, 1, ui8, ui8, ui8, , , , , linear, -R8G8B8_SINT , 24, 1, 1, 1, si8, si8, si8, , , , , linear, -RAW , 0, 0, 0, 0, , , , , , , , , diff --git a/src/isl/isl_format_layout_gen.bash b/src/isl/isl_format_layout_gen.bash deleted file mode 100755 index db883827376..00000000000 --- a/src/isl/isl_format_layout_gen.bash +++ /dev/null @@ -1,128 +0,0 @@ -#!/usr/bin/env bash -# -# Copyright 2015 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. - -set -eu -set -o pipefail - -cat <<'EOF' -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl.h" - -const struct isl_format_layout -isl_format_layouts[] = { -EOF - -sed -r ' -# Delete comment lines and empty lines -/^[[:space:]]*#/d -/^[[:space:]]*$/d - -# Delete spaces -s/[[:space:]]//g - -# Translate formats -s/^([A-Za-z0-9_]+),*/ISL_FORMAT_\1,/ - -# Translate data type of channels -s/\/ISL_COLORSPACE_\1/ -s/\// - -# Translate texture compression -s/\<(dxt|fxt|rgtc|bptc|etc)([0-9]*)\>/ISL_TXC_\1\2/ -' | -tr 'a-z' 'A-Z' | # Convert to uppersace -while IFS=, read -r format bpb bw bh bd \ - red green blue alpha \ - luminance intensity palette \ - colorspace txc -do - : ${colorspace:=ISL_COLORSPACE_NONE} - : ${txc:=ISL_TXC_NONE} - - cat <samples >= 1); - - *msaa_layout = ISL_MSAA_LAYOUT_NONE; - return true; -} - -void -gen4_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - assert(info->samples == 1); - assert(msaa_layout == ISL_MSAA_LAYOUT_NONE); - assert(!isl_tiling_is_std_y(tiling)); - - /* Note that neither the surface's horizontal nor vertical image alignment - * is programmable on gen4 nor gen5. - * - * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4 - * Alignment Unit Size: - * - * Note that the compressed formats are padded to a full compression - * cell. - * - * +------------------------+--------+--------+ - * | format | halign | valign | - * +------------------------+--------+--------+ - * | YUV 4:2:2 formats | 4 | 2 | - * | uncompressed formats | 4 | 2 | - * +------------------------+--------+--------+ - */ - - if (isl_format_is_compressed(info->format)) { - *image_align_el = isl_extent3d(1, 1, 1); - return; - } - - *image_align_el = isl_extent3d(4, 2, 1); -} diff --git a/src/isl/isl_gen4.h b/src/isl/isl_gen4.h deleted file mode 100644 index 06cd70b9206..00000000000 --- a/src/isl/isl_gen4.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include "isl_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -bool -gen4_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout); - -void -gen4_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_gen6.c b/src/isl/isl_gen6.c deleted file mode 100644 index 24c393925ed..00000000000 --- a/src/isl/isl_gen6.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl_gen6.h" -#include "isl_priv.h" - -bool -gen6_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - assert(ISL_DEV_GEN(dev) == 6); - assert(info->samples >= 1); - - if (info->samples == 1) { - *msaa_layout = ISL_MSAA_LAYOUT_NONE; - return false; - } - - /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface - * Format: - * - * If Number of Multisamples is set to a value other than - * MULTISAMPLECOUNT_1, this field cannot be set to the following - * formats: - * - * - any format with greater than 64 bits per element - * - any compressed texture format (BC*) - * - any YCRCB* format - */ - if (fmtl->bs > 8) - return false; - if (isl_format_is_compressed(info->format)) - return false; - if (isl_format_is_yuv(info->format)) - return false; - - /* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of - * Multisamples: - * - * If this field is any value other than MULTISAMPLECOUNT_1 the - * following restrictions apply: - * - * - the Surface Type must be SURFTYPE_2D - * - [...] - */ - if (info->dim != ISL_SURF_DIM_2D) - return false; - - /* More obvious restrictions */ - if (isl_surf_usage_is_display(info->usage)) - return false; - if (tiling == ISL_TILING_LINEAR) - return false; - if (info->levels > 1) - return false; - - *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; - return true; -} - -void -gen6_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - /* Note that the surface's horizontal image alignment is not programmable - * on Sandybridge. - * - * From the Sandybridge PRM (2011-05), Volume 1, Part 1, Section 7.18.3.4 - * Alignment Unit Size: - * - * Note that the compressed formats are padded to a full compression cell. - * - * +------------------------+--------+--------+ - * | format | halign | valign | - * +------------------------+--------+--------+ - * | YUV 4:2:2 formats | 4 | * | - * | uncompressed formats | 4 | * | - * +------------------------+--------+--------+ - * - * * For these formats, the vertical alignment factor “j” is determined - * as follows: - * - j = 4 for any depth buffer - * - j = 2 for separate stencil buffer - * - j = 4 for any render target surface is multisampled (4x) - * - j = 2 for all other render target surface - * - * From the Sandrybridge PRM (2011-05), Volume 4, Part 1, Section 2.11.2 - * SURFACE_STATE, Surface Vertical Alignment: - * - * - This field must be set to VALIGN_2 if the Surface Format is 96 bits - * per element (BPE). - * - * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL - * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY - * (0x190) - */ - - if (isl_format_is_compressed(info->format)) { - *image_align_el = isl_extent3d(1, 1, 1); - return; - } - - if (isl_format_is_yuv(info->format)) { - *image_align_el = isl_extent3d(4, 2, 1); - return; - } - - if (info->samples > 1) { - *image_align_el = isl_extent3d(4, 4, 1); - return; - } - - if (isl_surf_usage_is_depth_or_stencil(info->usage) && - !ISL_DEV_USE_SEPARATE_STENCIL(dev)) { - /* interleaved depthstencil buffer */ - *image_align_el = isl_extent3d(4, 4, 1); - return; - } - - if (isl_surf_usage_is_depth(info->usage)) { - /* separate depth buffer */ - *image_align_el = isl_extent3d(4, 4, 1); - return; - } - - if (isl_surf_usage_is_stencil(info->usage)) { - /* separate stencil buffer */ - *image_align_el = isl_extent3d(4, 2, 1); - return; - } - - *image_align_el = isl_extent3d(4, 2, 1); -} diff --git a/src/isl/isl_gen6.h b/src/isl/isl_gen6.h deleted file mode 100644 index 0779c674940..00000000000 --- a/src/isl/isl_gen6.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include "isl_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -bool -gen6_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout); - -void -gen6_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_gen7.c b/src/isl/isl_gen7.c deleted file mode 100644 index 7064e852e65..00000000000 --- a/src/isl/isl_gen7.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl_gen7.h" -#include "isl_priv.h" - -bool -gen7_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - bool require_array = false; - bool require_interleaved = false; - - assert(ISL_DEV_GEN(dev) == 7); - assert(info->samples >= 1); - - if (info->samples == 1) { - *msaa_layout = ISL_MSAA_LAYOUT_NONE; - return true; - } - - /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface - * Format: - * - * If Number of Multisamples is set to a value other than - * MULTISAMPLECOUNT_1, this field cannot be set to the following - * formats: any format with greater than 64 bits per element, any - * compressed texture format (BC*), and any YCRCB* format. - */ - if (fmtl->bs > 8) - return false; - if (isl_format_is_compressed(info->format)) - return false; - if (isl_format_is_yuv(info->format)) - return false; - - /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of - * Multisamples: - * - * - If this field is any value other than MULTISAMPLECOUNT_1, the - * Surface Type must be SURFTYPE_2D. - * - * - If this field is any value other than MULTISAMPLECOUNT_1, Surface - * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero - */ - if (info->dim != ISL_SURF_DIM_2D) - return false; - if (info->levels > 1) - return false; - - /* The Ivyrbridge PRM insists twice that signed integer formats cannot be - * multisampled. - * - * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of - * Multisamples: - * - * - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when - * all RT channels are not written. - * - * And errata from the Ivybridge PRM, Volume 4 Part 1 p77, - * RENDER_SURFACE_STATE, MCS Enable: - * - * This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs - * when all RT channels are not written. - * - * Note that the above SINT restrictions apply only to *MSRTs* (that is, - * *multisampled* render targets). The restrictions seem to permit an MCS - * if the render target is singlesampled. - */ - if (isl_format_has_sint_channel(info->format)) - return false; - - /* More obvious restrictions */ - if (isl_surf_usage_is_display(info->usage)) - return false; - if (tiling == ISL_TILING_LINEAR) - return false; - - /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled - * Suface Storage Format: - * - * +---------------------+----------------------------------------------------------------+ - * | MSFMT_MSS | Multsampled surface was/is rendered as a render target | - * | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer | - * +---------------------+----------------------------------------------------------------+ - * - * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and - * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED. - */ - if (isl_surf_usage_is_depth_or_stencil(info->usage)) - require_interleaved = true; - - /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled - * Suface Storage Format: - * - * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width - * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this - * field must be set to MSFMT_MSS. - */ - if (info->samples == 8 && info->width == 8192) - require_array = true; - - /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled - * Suface Storage Format: - * - * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, - * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number - * of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is - * > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL. - */ - if ((info->samples == 8 && info->height > 4194304u) || - (info->samples == 4 && info->height > 8388608u)) - require_interleaved = true; - - /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled - * Suface Storage Format: - * - * This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is - * one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or - * R24_UNORM_X8_TYPELESS. - */ - if (info->format == ISL_FORMAT_I24X8_UNORM || - info->format == ISL_FORMAT_L24X8_UNORM || - info->format == ISL_FORMAT_A24X8_UNORM || - info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) - require_interleaved = true; - - if (require_array && require_interleaved) - return false; - - if (require_interleaved) { - *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; - return true; - } - - /* Default to the array layout because it permits multisample - * compression. - */ - *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; - return true; -} - -static bool -gen7_format_needs_valign2(const struct isl_device *dev, - enum isl_format format) -{ - /* This workaround applies only to gen7 */ - if (ISL_DEV_GEN(dev) > 7) - return false; - - /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, - * RENDER_SURFACE_STATE Surface Vertical Alignment: - * - * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL - * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY - * (0x190) - * - * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT. - */ - return isl_format_is_yuv(format) || - format == ISL_FORMAT_R32G32B32_FLOAT; -} - -/** - * @brief Filter out tiling flags that are incompatible with the surface. - * - * The resultant outgoing @a flags is a subset of the incoming @a flags. The - * outgoing flags may be empty (0x0) if the incoming flags were too - * restrictive. - * - * For example, if the surface will be used for a display - * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling - * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT. - */ -void -gen7_filter_tiling(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - isl_tiling_flags_t *flags) -{ - /* IVB+ requires separate stencil */ - assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); - - /* Clear flags unsupported on this hardware */ - if (ISL_DEV_GEN(dev) < 9) { - *flags &= ~ISL_TILING_Yf_BIT; - *flags &= ~ISL_TILING_Ys_BIT; - } - - /* And... clear the Yf and Ys bits anyway because Anvil doesn't support - * them yet. - */ - *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */ - *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */ - - if (isl_surf_usage_is_depth(info->usage)) { - /* Depth requires Y. */ - *flags &= ISL_TILING_ANY_Y_MASK; - } - - /* Separate stencil requires W tiling, and W tiling requires separate - * stencil. - */ - if (isl_surf_usage_is_stencil(info->usage)) { - *flags &= ISL_TILING_W_BIT; - } else { - *flags &= ~ISL_TILING_W_BIT; - } - - if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | - ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | - ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { - assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); - isl_finishme("%s:%s: handle rotated display surfaces", - __FILE__, __func__); - } - - if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT | - ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) { - assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); - isl_finishme("%s:%s: handle flipped display surfaces", - __FILE__, __func__); - } - - if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) { - /* Before Skylake, the display engine does not accept Y */ - /* FINISHME[SKL]: Y tiling for display surfaces */ - *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT); - } - - if (info->samples > 1) { - /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled - * Surface: - * - * For multisample render targets, this field must be 1 (true). MSRTs - * can only be tiled. - * - * Multisample surfaces never require X tiling, and Y tiling generally - * performs better than X. So choose Y. (Unless it's stencil, then it - * must be W). - */ - *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT); - } - - /* workaround */ - if (ISL_DEV_GEN(dev) == 7 && - gen7_format_needs_valign2(dev, info->format) && - (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && - info->samples == 1) { - /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1, - * SURFACE_STATE Surface Vertical Alignment: - * - * This field must be set to VALIGN_4 for all tiled Y Render Target - * surfaces. - */ - *flags &= ~ISL_TILING_Y0_BIT; - } -} - -/** - * Choose horizontal subimage alignment, in units of surface elements. - */ -static uint32_t -gen7_choose_halign_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info) -{ - if (isl_format_is_compressed(info->format)) - return 1; - - /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, - * RENDER_SURFACE_STATE Surface Hoizontal Alignment: - * - * - This field is intended to be set to HALIGN_8 only if the surface - * was rendered as a depth buffer with Z16 format or a stencil buffer, - * since these surfaces support only alignment of 8. Use of HALIGN_8 - * for other surfaces is supported, but uses more memory. - */ - if (isl_surf_info_is_z16(info) || - isl_surf_usage_is_stencil(info->usage)) - return 8; - - return 4; -} - -/** - * Choose vertical subimage alignment, in units of surface elements. - */ -static uint32_t -gen7_choose_valign_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling) -{ - bool require_valign2 = false; - bool require_valign4 = false; - - if (isl_format_is_compressed(info->format)) - return 1; - - if (gen7_format_needs_valign2(dev, info->format)) - require_valign2 = true; - - /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1: - * RENDER_SURFACE_STATE Surface Vertical Alignment: - * - * - This field is intended to be set to VALIGN_4 if the surface was - * rendered as a depth buffer, for a multisampled (4x) render target, - * or for a multisampled (8x) render target, since these surfaces - * support only alignment of 4. Use of VALIGN_4 for other surfaces is - * supported, but uses more memory. This field must be set to - * VALIGN_4 for all tiled Y Render Target surfaces. - * - */ - if (isl_surf_usage_is_depth(info->usage) || - info->samples > 1 || - tiling == ISL_TILING_Y0) { - require_valign4 = true; - } - - if (isl_surf_usage_is_stencil(info->usage)) { - /* The Ivybridge PRM states that the stencil buffer's vertical alignment - * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment - * Unit Size]. However, valign=8 is outside the set of valid values of - * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2 - * (0x0) and VALIGN_4 (0x1). - * - * The PRM is generally confused about the width, height, and alignment - * of the stencil buffer; and this confusion appears elsewhere. For - * example, the following PRM text effectively converts the stencil - * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM, - * Volume 1, Part 1, Section - * 6.18.4.2 Base Address and LOD Calculation]: - * - * For separate stencil buffer, the width must be mutiplied by 2 and - * height divided by 2 as follows: - * - * w_L = 2*i*ceil(W_L/i) - * h_L = 1/2*j*ceil(H_L/j) - * - * The root of the confusion is that, in W tiling, each pair of rows is - * interleaved into one. - * - * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API - * is more polished. - */ - require_valign4 = true; - } - - assert(!require_valign2 || !require_valign4); - - if (require_valign4) - return 4; - - /* Prefer VALIGN_2 because it conserves memory. */ - return 2; -} - -void -gen7_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - /* IVB+ does not support combined depthstencil. */ - assert(!isl_surf_usage_is_depth_and_stencil(info->usage)); - - *image_align_el = (struct isl_extent3d) { - .w = gen7_choose_halign_el(dev, info), - .h = gen7_choose_valign_el(dev, info, tiling), - .d = 1, - }; -} diff --git a/src/isl/isl_gen7.h b/src/isl/isl_gen7.h deleted file mode 100644 index 2a95b68a9bd..00000000000 --- a/src/isl/isl_gen7.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include "isl_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void -gen7_filter_tiling(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - isl_tiling_flags_t *flags); - -bool -gen7_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout); - -void -gen7_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_gen8.c b/src/isl/isl_gen8.c deleted file mode 100644 index a46427aacc8..00000000000 --- a/src/isl/isl_gen8.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl_gen8.h" -#include "isl_priv.h" - -bool -gen8_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout) -{ - bool require_array = false; - bool require_interleaved = false; - - assert(info->samples >= 1); - - if (info->samples == 1) { - *msaa_layout = ISL_MSAA_LAYOUT_NONE; - return true; - } - - /* From the Broadwell PRM >> Volume2d: Command Structures >> - * RENDER_SURFACE_STATE Tile Mode: - * - * - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field - * must be YMAJOR. - * - * As usual, though, stencil is special. - */ - if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage)) - return false; - - /* From the Broadwell PRM >> Volume2d: Command Structures >> - * RENDER_SURFACE_STATE Multisampled Surface Storage Format: - * - * All multisampled render target surfaces must have this field set to - * MSFMT_MSS - */ - if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) - require_array = true; - - /* From the Broadwell PRM >> Volume2d: Command Structures >> - * RENDER_SURFACE_STATE Number of Multisamples: - * - * - If this field is any value other than MULTISAMPLECOUNT_1, the - * Surface Type must be SURFTYPE_2D This field must be set to - * MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface - * or Render Target surface. - * - * - If this field is any value other than MULTISAMPLECOUNT_1, Surface - * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero. - */ - if (info->dim != ISL_SURF_DIM_2D) - return false; - if (info->levels > 1) - return false; - - /* More obvious restrictions */ - if (isl_surf_usage_is_display(info->usage)) - return false; - if (isl_format_is_compressed(info->format)) - return false; - if (isl_format_is_yuv(info->format)) - return false; - - if (isl_surf_usage_is_depth_or_stencil(info->usage)) - require_interleaved = true; - - if (require_array && require_interleaved) - return false; - - if (require_interleaved) { - *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; - return true; - } - - *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; - return true; -} - -/** - * Choose horizontal subimage alignment, in units of surface elements. - */ -static uint32_t -gen8_choose_halign_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info) -{ - if (isl_format_is_compressed(info->format)) - return 1; - - /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", - * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: - * - * - This field is intended to be set to HALIGN_8 only if the surface - * was rendered as a depth buffer with Z16 format or a stencil buffer. - * In this case it must be set to HALIGN_8 since these surfaces - * support only alignment of 8. [...] - */ - if (isl_surf_info_is_z16(info)) - return 8; - if (isl_surf_usage_is_stencil(info->usage)) - return 8; - - /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", - * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: - * - * [...] For Z32 formats it must be set to HALIGN_4. - */ - if (isl_surf_usage_is_depth(info->usage)) - return 4; - - if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { - /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", - * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: - * - * - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, - * HALIGN 16 must be used. - * - * This case handles color surfaces that may own an auxiliary MCS, CCS_D, - * or CCS_E. Depth buffers, including those that own an auxiliary HiZ - * surface, are handled above and do not require HALIGN_16. - */ - assert(!isl_surf_usage_is_depth(info->usage)); - return 16; - } - - /* XXX(chadv): I believe the hardware requires each image to be - * cache-aligned. If that's true, then defaulting to halign=4 is wrong for - * many formats. Depending on the format's block size, we may need to - * increase halign to 8. - */ - return 4; -} - -/** - * Choose vertical subimage alignment, in units of surface elements. - */ -static uint32_t -gen8_choose_valign_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info) -{ - /* From the Broadwell PRM > Volume 2d: Command Reference: Structures - * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325): - * - * - For Sampling Engine and Render Target Surfaces: This field - * specifies the vertical alignment requirement in elements for the - * surface. [...] An element is defined as a pixel in uncompresed - * surface formats, and as a compression block in compressed surface - * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an - * element is a sample. - * - * - This field is intended to be set to VALIGN_4 if the surface was - * rendered as a depth buffer, for a multisampled (4x) render target, - * or for a multisampled (8x) render target, since these surfaces - * support only alignment of 4. Use of VALIGN_4 for other surfaces is - * supported, but increases memory usage. - * - * - This field is intended to be set to VALIGN_8 only if the surface - * was rendered as a stencil buffer, since stencil buffer surfaces - * support only alignment of 8. If set to VALIGN_8, Surface Format - * must be R8_UINT. - */ - - if (isl_format_is_compressed(info->format)) - return 1; - - if (isl_surf_usage_is_stencil(info->usage)) - return 8; - - return 4; -} - -void -gen8_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - assert(!isl_tiling_is_std_y(tiling)); - - /* The below text from the Broadwell PRM provides some insight into the - * hardware's requirements for LOD alignment. From the Broadwell PRM >> - * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: - * - * These [2D surfaces] must adhere to the following memory organization - * rules: - * - * - For non-compressed texture formats, each mipmap must start on an - * even row within the monolithic rectangular area. For - * 1-texel-high mipmaps, this may require a row of padding below - * the previous mipmap. This restriction does not apply to any - * compressed texture formats; each subsequent (lower-res) - * compressed mipmap is positioned directly below the previous - * mipmap. - * - * - Vertical alignment restrictions vary with memory tiling type: - * 1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled - * mipmaps are not required to start at the left edge of a tile - * row.) - */ - - *image_align_el = (struct isl_extent3d) { - .w = gen8_choose_halign_el(dev, info), - .h = gen8_choose_valign_el(dev, info), - .d = 1, - }; -} diff --git a/src/isl/isl_gen8.h b/src/isl/isl_gen8.h deleted file mode 100644 index 2017ea8ddc1..00000000000 --- a/src/isl/isl_gen8.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include "isl_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -bool -gen8_choose_msaa_layout(const struct isl_device *dev, - const struct isl_surf_init_info *info, - enum isl_tiling tiling, - enum isl_msaa_layout *msaa_layout); - -void -gen8_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_gen9.c b/src/isl/isl_gen9.c deleted file mode 100644 index aa290aa1c35..00000000000 --- a/src/isl/isl_gen9.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl_gen8.h" -#include "isl_gen9.h" -#include "isl_priv.h" - -/** - * Calculate the surface's subimage alignment, in units of surface samples, - * for the standard tiling formats Yf and Ys. - */ -static void -gen9_calc_std_image_alignment_sa(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *align_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); - - assert(isl_tiling_is_std_y(tiling)); - - const uint32_t bs = fmtl->bs; - const uint32_t is_Ys = tiling == ISL_TILING_Ys; - - switch (info->dim) { - case ISL_SURF_DIM_1D: - /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface - * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. - */ - *align_sa = (struct isl_extent3d) { - .w = 1 << (12 - (ffs(bs) - 1) + (4 * is_Ys)), - .h = 1, - .d = 1, - }; - return; - case ISL_SURF_DIM_2D: - /* See the Skylake BSpec > Memory Views > Common Surface Formats > - * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment - * Requirements. - */ - *align_sa = (struct isl_extent3d) { - .w = 1 << (6 - ((ffs(bs) - 1) / 2) + (4 * is_Ys)), - .h = 1 << (6 - ((ffs(bs) - 0) / 2) + (4 * is_Ys)), - .d = 1, - }; - - if (is_Ys) { - /* FINISHME(chadv): I don't trust this code. Untested. */ - isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__); - - switch (msaa_layout) { - case ISL_MSAA_LAYOUT_NONE: - case ISL_MSAA_LAYOUT_INTERLEAVED: - break; - case ISL_MSAA_LAYOUT_ARRAY: - align_sa->w >>= (ffs(info->samples) - 0) / 2; - align_sa->h >>= (ffs(info->samples) - 1) / 2; - break; - } - } - return; - - case ISL_SURF_DIM_3D: - /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface - * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. - */ - *align_sa = (struct isl_extent3d) { - .w = 1 << (4 - ((ffs(bs) + 1) / 3) + (4 * is_Ys)), - .h = 1 << (4 - ((ffs(bs) - 1) / 3) + (2 * is_Ys)), - .d = 1 << (4 - ((ffs(bs) - 0) / 3) + (2 * is_Ys)), - }; - return; - } - - unreachable("bad isl_surface_type"); -} - -void -gen9_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el) -{ - /* This BSpec text provides some insight into the hardware's alignment - * requirements [Skylake BSpec > Memory Views > Common Surface Formats > - * Surface Layout and Tiling > 2D Surfaces]: - * - * An LOD must be aligned to a cache-line except for some special cases - * related to Planar YUV surfaces. In general, the cache-alignment - * restriction implies there is a minimum height for an LOD of 4 texels. - * So, LODs which are smaller than 4 high are padded. - * - * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment: - * - * - For Sampling Engine and Render Target Surfaces: This field - * specifies the vertical alignment requirement in elements for the - * surface. [...] An element is defined as a pixel in uncompresed - * surface formats, and as a compression block in compressed surface - * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an - * element is a sample. - * - * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled - * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled). - * This field is ignored for 1D surfaces and also when Tiled Resource - * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled). - * - * See the appropriate Alignment table in the "Surface Layout and - * Tiling" section under Common Surface Formats for the table of - * alignment values for Tiled Resrouces. - * - * - For uncompressed surfaces, the units of "j" are rows of pixels on - * the physical surface. For compressed texture formats, the units of - * "j" are in compression blocks, thus each increment in "j" is equal - * to h pixels, where h is the height of the compression block in - * pixels. - * - * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16 - * - * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal - * Alignment: - * - * - For uncompressed surfaces, the units of "i" are pixels on the - * physical surface. For compressed texture formats, the units of "i" - * are in compression blocks, thus each increment in "i" is equal to - * w pixels, where w is the width of the compression block in pixels. - * - * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16 - */ - - if (isl_tiling_is_std_y(tiling)) { - struct isl_extent3d image_align_sa; - gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, - &image_align_sa); - - *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa); - return; - } - - if (info->dim == ISL_SURF_DIM_1D) { - /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface - * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. - */ - *image_align_el = isl_extent3d(64, 1, 1); - return; - } - - if (isl_format_is_compressed(info->format)) { - /* On Gen9, the meaning of RENDER_SURFACE_STATE's - * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for - * compressed formats. They now indicate a multiple of the compression - * block. For example, if the compression mode is ETC2 then HALIGN_4 - * indicates a horizontal alignment of 16 pixels. - * - * To avoid wasting memory, choose the smallest alignment possible: - * HALIGN_4 and VALIGN_4. - */ - *image_align_el = isl_extent3d(4, 4, 1); - return; - } - - gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout, - image_align_el); -} diff --git a/src/isl/isl_gen9.h b/src/isl/isl_gen9.h deleted file mode 100644 index 64ed0aa44ef..00000000000 --- a/src/isl/isl_gen9.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include "isl_priv.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void -gen9_choose_image_alignment_el(const struct isl_device *dev, - const struct isl_surf_init_info *restrict info, - enum isl_tiling tiling, - enum isl_msaa_layout msaa_layout, - struct isl_extent3d *image_align_el); - -#ifdef __cplusplus -} -#endif diff --git a/src/isl/isl_image.c b/src/isl/isl_image.c deleted file mode 100644 index 773160432b9..00000000000 --- a/src/isl/isl_image.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "isl.h" -#include "brw_compiler.h" - -bool -isl_is_storage_image_format(enum isl_format format) -{ - /* XXX: Maybe we should put this in the CSV? */ - - switch (format) { - case ISL_FORMAT_R32G32B32A32_UINT: - case ISL_FORMAT_R32G32B32A32_SINT: - case ISL_FORMAT_R32G32B32A32_FLOAT: - case ISL_FORMAT_R32_UINT: - case ISL_FORMAT_R32_SINT: - case ISL_FORMAT_R32_FLOAT: - case ISL_FORMAT_R16G16B16A16_UINT: - case ISL_FORMAT_R16G16B16A16_SINT: - case ISL_FORMAT_R16G16B16A16_FLOAT: - case ISL_FORMAT_R32G32_UINT: - case ISL_FORMAT_R32G32_SINT: - case ISL_FORMAT_R32G32_FLOAT: - case ISL_FORMAT_R8G8B8A8_UINT: - case ISL_FORMAT_R8G8B8A8_SINT: - case ISL_FORMAT_R16G16_UINT: - case ISL_FORMAT_R16G16_SINT: - case ISL_FORMAT_R16G16_FLOAT: - case ISL_FORMAT_R8G8_UINT: - case ISL_FORMAT_R8G8_SINT: - case ISL_FORMAT_R16_UINT: - case ISL_FORMAT_R16_FLOAT: - case ISL_FORMAT_R16_SINT: - case ISL_FORMAT_R8_UINT: - case ISL_FORMAT_R8_SINT: - case ISL_FORMAT_R10G10B10A2_UINT: - case ISL_FORMAT_R10G10B10A2_UNORM: - case ISL_FORMAT_R11G11B10_FLOAT: - case ISL_FORMAT_R16G16B16A16_UNORM: - case ISL_FORMAT_R16G16B16A16_SNORM: - case ISL_FORMAT_R8G8B8A8_UNORM: - case ISL_FORMAT_R8G8B8A8_SNORM: - case ISL_FORMAT_R16G16_UNORM: - case ISL_FORMAT_R16G16_SNORM: - case ISL_FORMAT_R8G8_UNORM: - case ISL_FORMAT_R8G8_SNORM: - case ISL_FORMAT_R16_UNORM: - case ISL_FORMAT_R16_SNORM: - case ISL_FORMAT_R8_UNORM: - case ISL_FORMAT_R8_SNORM: - return true; - default: - return false; - } -} - -enum isl_format -isl_lower_storage_image_format(const struct isl_device *dev, - enum isl_format format) -{ - switch (format) { - /* These are never lowered. Up to BDW we'll have to fall back to untyped - * surface access for 128bpp formats. - */ - case ISL_FORMAT_R32G32B32A32_UINT: - case ISL_FORMAT_R32G32B32A32_SINT: - case ISL_FORMAT_R32G32B32A32_FLOAT: - case ISL_FORMAT_R32_UINT: - case ISL_FORMAT_R32_SINT: - case ISL_FORMAT_R32_FLOAT: - return format; - - /* From HSW to BDW the only 64bpp format supported for typed access is - * RGBA_UINT16. IVB falls back to untyped. - */ - case ISL_FORMAT_R16G16B16A16_UINT: - case ISL_FORMAT_R16G16B16A16_SINT: - case ISL_FORMAT_R16G16B16A16_FLOAT: - case ISL_FORMAT_R32G32_UINT: - case ISL_FORMAT_R32G32_SINT: - case ISL_FORMAT_R32G32_FLOAT: - return (ISL_DEV_GEN(dev) >= 9 ? format : - ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R16G16B16A16_UINT : - ISL_FORMAT_R32G32_UINT); - - /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component - * are supported. IVB doesn't support formats with more than one component - * for typed access. For 8 and 16 bpp formats IVB relies on the - * undocumented behavior that typed reads from R_UINT8 and R_UINT16 - * surfaces actually do a 32-bit misaligned read. The alternative would be - * to use two surface state entries with different formats for each image, - * one for reading (using R_UINT32) and another one for writing (using - * R_UINT8 or R_UINT16), but that would complicate the shaders we generate - * even more. - */ - case ISL_FORMAT_R8G8B8A8_UINT: - case ISL_FORMAT_R8G8B8A8_SINT: - return (ISL_DEV_GEN(dev) >= 9 ? format : - ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); - - case ISL_FORMAT_R16G16_UINT: - case ISL_FORMAT_R16G16_SINT: - case ISL_FORMAT_R16G16_FLOAT: - return (ISL_DEV_GEN(dev) >= 9 ? format : - ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); - - case ISL_FORMAT_R8G8_UINT: - case ISL_FORMAT_R8G8_SINT: - return (ISL_DEV_GEN(dev) >= 9 ? format : - ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); - - case ISL_FORMAT_R16_UINT: - case ISL_FORMAT_R16_FLOAT: - case ISL_FORMAT_R16_SINT: - return (ISL_DEV_GEN(dev) >= 9 ? format : ISL_FORMAT_R16_UINT); - - case ISL_FORMAT_R8_UINT: - case ISL_FORMAT_R8_SINT: - return (ISL_DEV_GEN(dev) >= 9 ? format : ISL_FORMAT_R8_UINT); - - /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported - * by the hardware. - */ - case ISL_FORMAT_R10G10B10A2_UINT: - case ISL_FORMAT_R10G10B10A2_UNORM: - case ISL_FORMAT_R11G11B10_FLOAT: - return ISL_FORMAT_R32_UINT; - - /* No normalized fixed-point formats are supported by the hardware. */ - case ISL_FORMAT_R16G16B16A16_UNORM: - case ISL_FORMAT_R16G16B16A16_SNORM: - return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R16G16B16A16_UINT : - ISL_FORMAT_R32G32_UINT); - - case ISL_FORMAT_R8G8B8A8_UNORM: - case ISL_FORMAT_R8G8B8A8_SNORM: - return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); - - case ISL_FORMAT_R16G16_UNORM: - case ISL_FORMAT_R16G16_SNORM: - return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); - - case ISL_FORMAT_R8G8_UNORM: - case ISL_FORMAT_R8G8_SNORM: - return (ISL_DEV_GEN(dev) >= 8 || dev->info->is_haswell ? - ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); - - case ISL_FORMAT_R16_UNORM: - case ISL_FORMAT_R16_SNORM: - return ISL_FORMAT_R16_UINT; - - case ISL_FORMAT_R8_UNORM: - case ISL_FORMAT_R8_SNORM: - return ISL_FORMAT_R8_UINT; - - default: - assert(!"Unknown image format"); - return ISL_FORMAT_UNSUPPORTED; - } -} diff --git a/src/isl/isl_priv.h b/src/isl/isl_priv.h deleted file mode 100644 index b399e0f8116..00000000000 --- a/src/isl/isl_priv.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include - -#include "brw_device_info.h" -#include "mesa/main/imports.h" -#include "util/macros.h" - -#include "isl.h" - -#define isl_finishme(format, ...) \ - __isl_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__) - -void PRINTFLIKE(3, 4) UNUSED -__isl_finishme(const char *file, int line, const char *fmt, ...); - -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -static inline uint32_t -ffs(uint32_t n) { - return __builtin_ffs(n); -} - -static inline bool -isl_is_pow2(uintmax_t n) -{ - return !(n & (n - 1)); -} - -/** - * Alignment must be a power of 2. - */ -static inline bool -isl_is_aligned(uintmax_t n, uintmax_t a) -{ - assert(isl_is_pow2(a)); - return (n & (a - 1)) == 0; -} - -/** - * Alignment must be a power of 2. - */ -static inline uintmax_t -isl_align(uintmax_t n, uintmax_t a) -{ - assert(a != 0 && isl_is_pow2(a)); - return (n + a - 1) & ~(a - 1); -} - -static inline uintmax_t -isl_align_npot(uintmax_t n, uintmax_t a) -{ - assert(a > 0); - return ((n + a - 1) / a) * a; -} - -/** - * Alignment must be a power of 2. - */ -static inline uintmax_t -isl_align_div(uintmax_t n, uintmax_t a) -{ - return isl_align(n, a) / a; -} - -static inline uintmax_t -isl_align_div_npot(uintmax_t n, uintmax_t a) -{ - return isl_align_npot(n, a) / a; -} - -/** - * Log base 2, rounding towards zero. - */ -static inline uint32_t -isl_log2u(uint32_t n) -{ - assert(n != 0); - return 31 - __builtin_clz(n); -} - -static inline uint32_t -isl_minify(uint32_t n, uint32_t levels) -{ - if (unlikely(n == 0)) - return 0; - else - return MAX(n >> levels, 1); -} - -static inline struct isl_extent3d -isl_extent3d_sa_to_el(enum isl_format fmt, struct isl_extent3d extent_sa) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - assert(extent_sa.w % fmtl->bw == 0); - assert(extent_sa.h % fmtl->bh == 0); - assert(extent_sa.d % fmtl->bd == 0); - - return (struct isl_extent3d) { - .w = extent_sa.w / fmtl->bw, - .h = extent_sa.h / fmtl->bh, - .d = extent_sa.d / fmtl->bd, - }; -} - -static inline struct isl_extent3d -isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el) -{ - const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); - - return (struct isl_extent3d) { - .w = extent_el.w * fmtl->bw, - .h = extent_el.h * fmtl->bh, - .d = extent_el.d * fmtl->bd, - }; -} diff --git a/src/isl/tests/.gitignore b/src/isl/tests/.gitignore deleted file mode 100644 index ba70ecfbee4..00000000000 --- a/src/isl/tests/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/isl_surf_get_image_offset_test diff --git a/src/isl/tests/isl_surf_get_image_offset_test.c b/src/isl/tests/isl_surf_get_image_offset_test.c deleted file mode 100644 index cda8583daeb..00000000000 --- a/src/isl/tests/isl_surf_get_image_offset_test.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "brw_device_info.h" -#include "isl.h" -#include "isl_priv.h" - -#define BDW_GT2_DEVID 0x161a - -// An asssert that works regardless of NDEBUG. -#define t_assert(cond) \ - do { \ - if (!(cond)) { \ - fprintf(stderr, "%s:%d: assertion failed\n", __FILE__, __LINE__); \ - abort(); \ - } \ - } while (0) - -static void -t_assert_extent4d(const struct isl_extent4d *e, uint32_t width, - uint32_t height, uint32_t depth, uint32_t array_len) -{ - t_assert(e->width == width); - t_assert(e->height == height); - t_assert(e->depth == depth); - t_assert(e->array_len == array_len); -} - -static void -t_assert_image_alignment_el(const struct isl_surf *surf, - uint32_t w, uint32_t h, uint32_t d) -{ - struct isl_extent3d align_el; - - align_el = isl_surf_get_image_alignment_el(surf); - t_assert(align_el.w == w); - t_assert(align_el.h == h); - t_assert(align_el.d == d); - -} - -static void -t_assert_image_alignment_sa(const struct isl_surf *surf, - uint32_t w, uint32_t h, uint32_t d) -{ - struct isl_extent3d align_sa; - - align_sa = isl_surf_get_image_alignment_sa(surf); - t_assert(align_sa.w == w); - t_assert(align_sa.h == h); - t_assert(align_sa.d == d); - -} - -static void -t_assert_offset_el(const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset_px, - uint32_t expected_x_offset_el, - uint32_t expected_y_offset_el) -{ - uint32_t x, y; - isl_surf_get_image_offset_el(surf, level, logical_array_layer, - logical_z_offset_px, &x, &y); - - t_assert(x == expected_x_offset_el); - t_assert(y == expected_y_offset_el); -} - -static void -t_assert_intratile_offset_el(const struct isl_device *dev, - const struct isl_surf *surf, - uint32_t level, - uint32_t logical_array_layer, - uint32_t logical_z_offset_px, - uint32_t expected_base_address_offset, - uint32_t expected_x_offset_el, - uint32_t expected_y_offset_el) -{ - uint32_t base_address_offset; - uint32_t x_offset_el, y_offset_el; - isl_surf_get_image_intratile_offset_el(dev, surf, - level, - logical_array_layer, - logical_z_offset_px, - &base_address_offset, - &x_offset_el, - &y_offset_el); - - t_assert(base_address_offset == expected_base_address_offset); - t_assert(x_offset_el == expected_x_offset_el); - t_assert(y_offset_el == expected_y_offset_el); -} - -static void -t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width, - uint32_t height, uint32_t depth, uint32_t array_len) -{ - t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len); -} - -static void -t_assert_gen4_3d_layer(const struct isl_surf *surf, - uint32_t level, - uint32_t aligned_width, - uint32_t aligned_height, - uint32_t depth, - uint32_t horiz_layers, - uint32_t vert_layers, - uint32_t *base_y) -{ - for (uint32_t z = 0; z < depth; ++z) { - t_assert_offset_el(surf, level, 0, z, - aligned_width * (z % horiz_layers), - *base_y + aligned_height * (z / horiz_layers)); - } - - *base_y += aligned_height * vert_layers; -} - -static void -test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void) -{ - bool ok; - - struct isl_device dev; - isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), - /*bit6_swizzle*/ false); - - struct isl_surf surf; - ok = isl_surf_init(&dev, &surf, - .dim = ISL_SURF_DIM_2D, - .format = ISL_FORMAT_R8G8B8A8_UNORM, - .width = 512, - .height = 512, - .depth = 1, - .levels = 10, - .array_len = 1, - .samples = 1, - .usage = ISL_SURF_USAGE_TEXTURE_BIT | - ISL_SURF_USAGE_DISABLE_AUX_BIT, - .tiling_flags = ISL_TILING_Y0_BIT); - t_assert(ok); - - t_assert_image_alignment_el(&surf, 4, 4, 1); - t_assert_image_alignment_sa(&surf, 4, 4, 1); - t_assert_phys_level0_sa(&surf, 512, 512, 1, 1); - t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 772); - t_assert(isl_surf_get_array_pitch_el_rows(&surf) == - isl_surf_get_array_pitch_sa_rows(&surf)); - - /* Row pitch should be minimal possible */ - t_assert(surf.row_pitch == 2048); - - t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0 - t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512 - t_assert_offset_el(&surf, 2, 0, 0, 256, 512); // +256, +0 - t_assert_offset_el(&surf, 3, 0, 0, 256, 640); // +0, +128 - t_assert_offset_el(&surf, 4, 0, 0, 256, 704); // +0, +64 - t_assert_offset_el(&surf, 5, 0, 0, 256, 736); // +0, +32 - t_assert_offset_el(&surf, 6, 0, 0, 256, 752); // +0, +16 - t_assert_offset_el(&surf, 7, 0, 0, 256, 760); // +0, +8 - t_assert_offset_el(&surf, 8, 0, 0, 256, 764); // +0, +4 - t_assert_offset_el(&surf, 9, 0, 0, 256, 768); // +0, +4 - - t_assert_intratile_offset_el(&dev, &surf, 0, 0, 0, 0x0, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 1, 0, 0, 0x100000, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 2, 0, 0, 0x100400, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 3, 0, 0, 0x140400, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 4, 0, 0, 0x160400, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 5, 0, 0, 0x170400, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 6, 0, 0, 0x170400, 0, 16); - t_assert_intratile_offset_el(&dev, &surf, 7, 0, 0, 0x170400, 0, 24); - t_assert_intratile_offset_el(&dev, &surf, 8, 0, 0, 0x170400, 0, 28); - t_assert_intratile_offset_el(&dev, &surf, 9, 0, 0, 0x180400, 0, 0); -} - -static void -test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void) -{ - bool ok; - - struct isl_device dev; - isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), - /*bit6_swizzle*/ false); - - struct isl_surf surf; - ok = isl_surf_init(&dev, &surf, - .dim = ISL_SURF_DIM_2D, - .format = ISL_FORMAT_R8G8B8A8_UNORM, - .width = 1024, - .height = 1024, - .depth = 1, - .levels = 11, - .array_len = 6, - .samples = 1, - .usage = ISL_SURF_USAGE_TEXTURE_BIT | - ISL_SURF_USAGE_DISABLE_AUX_BIT, - .tiling_flags = ISL_TILING_Y0_BIT); - t_assert(ok); - - t_assert_image_alignment_el(&surf, 4, 4, 1); - t_assert_image_alignment_sa(&surf, 4, 4, 1); - - t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 1540); - t_assert(isl_surf_get_array_pitch_el_rows(&surf) == - isl_surf_get_array_pitch_sa_rows(&surf)); - - /* Row pitch should be minimal possible */ - t_assert(surf.row_pitch == 4096); - - for (uint32_t a = 0; a < 6; ++a) { - uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf); - - t_assert_offset_el(&surf, 0, a, 0, 0, b + 0); // +0, +0 - t_assert_offset_el(&surf, 1, a, 0, 0, b + 1024); // +0, +1024 - t_assert_offset_el(&surf, 2, a, 0, 512, b + 1024); // +512, +0 - t_assert_offset_el(&surf, 3, a, 0, 512, b + 1280); // +0, +256 - t_assert_offset_el(&surf, 4, a, 0, 512, b + 1408); // +0, +128 - t_assert_offset_el(&surf, 5, a, 0, 512, b + 1472); // +0, +64 - t_assert_offset_el(&surf, 6, a, 0, 512, b + 1504); // +0, +32 - t_assert_offset_el(&surf, 7, a, 0, 512, b + 1520); // +0, +16 - t_assert_offset_el(&surf, 8, a, 0, 512, b + 1528); // +0, +8 - t_assert_offset_el(&surf, 9, a, 0, 512, b + 1532); // +0, +4 - t_assert_offset_el(&surf, 10, a, 0, 512, b + 1536); // +0, +4 - - } - - /* The layout below assumes a specific array pitch. It will need updating - * if isl's array pitch calculations ever change. - */ - t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 1540); - - /* array layer 0 */ - t_assert_intratile_offset_el(&dev, &surf, 0, 0, 0, 0x0, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 1, 0, 0, 0x400000, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 2, 0, 0, 0x400800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 3, 0, 0, 0x500800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 4, 0, 0, 0x580800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 5, 0, 0, 0x5c0800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 6, 0, 0, 0x5e0800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 7, 0, 0, 0x5e0800, 0, 16); - t_assert_intratile_offset_el(&dev, &surf, 8, 0, 0, 0x5e0800, 0, 24); - t_assert_intratile_offset_el(&dev, &surf, 9, 0, 0, 0x5e0800, 0, 28); - t_assert_intratile_offset_el(&dev, &surf, 10, 0, 0, 0x600800, 0, 0); - - /* array layer 1 */ - t_assert_intratile_offset_el(&dev, &surf, 0, 1, 0, 0x600000, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 1, 1, 0, 0xa00000, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 2, 1, 0, 0xa00800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 3, 1, 0, 0xb00800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 4, 1, 0, 0xb80800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 5, 1, 0, 0xbc0800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 6, 1, 0, 0xbe0800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 7, 1, 0, 0xbe0800, 0, 20); - t_assert_intratile_offset_el(&dev, &surf, 8, 1, 0, 0xbe0800, 0, 28); - t_assert_intratile_offset_el(&dev, &surf, 9, 1, 0, 0xc00800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 10, 1, 0, 0xc00800, 0, 4); - - /* array layer 2 */ - t_assert_intratile_offset_el(&dev, &surf, 0, 2, 0, 0xc00000, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 1, 2, 0, 0x1000000, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 2, 2, 0, 0x1000800, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 3, 2, 0, 0x1100800, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 4, 2, 0, 0x1180800, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 5, 2, 0, 0x11c0800, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 6, 2, 0, 0x11e0800, 0, 8); - t_assert_intratile_offset_el(&dev, &surf, 7, 2, 0, 0x11e0800, 0, 24); - t_assert_intratile_offset_el(&dev, &surf, 8, 2, 0, 0x1200800, 0, 0); - t_assert_intratile_offset_el(&dev, &surf, 9, 2, 0, 0x1200800, 0, 4); - t_assert_intratile_offset_el(&dev, &surf, 10, 2, 0, 0x1200800, 0, 8); - - /* skip the remaining array layers */ -} - -static void -test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void) -{ - bool ok; - - struct isl_device dev; - isl_device_init(&dev, brw_get_device_info(BDW_GT2_DEVID), - /*bit6_swizzle*/ false); - - struct isl_surf surf; - ok = isl_surf_init(&dev, &surf, - .dim = ISL_SURF_DIM_3D, - .format = ISL_FORMAT_R8G8B8A8_UNORM, - .width = 256, - .height = 256, - .depth = 256, - .levels = 9, - .array_len = 1, - .samples = 1, - .usage = ISL_SURF_USAGE_TEXTURE_BIT | - ISL_SURF_USAGE_DISABLE_AUX_BIT, - .tiling_flags = ISL_TILING_Y0_BIT); - t_assert(ok); - - t_assert_image_alignment_el(&surf, 4, 4, 1); - t_assert_image_alignment_sa(&surf, 4, 4, 1); - t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 74916); - t_assert(isl_surf_get_array_pitch_sa_rows(&surf) == - isl_surf_get_array_pitch_el_rows(&surf)); - - uint32_t base_y = 0; - - t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y); - t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y); - t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y); - t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y); - t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y); - t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y); -} - -int main(void) -{ - /* FINISHME: Add tests for npot sizes */ - /* FINISHME: Add tests for 1D surfaces */ - - test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(); - test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(); - test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(); -} diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am index 50d972e6c7e..0605dc437d7 100644 --- a/src/vulkan/Makefile.am +++ b/src/vulkan/Makefile.am @@ -62,7 +62,6 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/src/gallium/auxiliary \ -I$(top_srcdir)/src/gallium/include \ -I$(top_srcdir)/src/intel/ \ - -I$(top_srcdir)/src/isl/ \ -I$(top_builddir)/src \ -I$(top_builddir)/src/compiler \ -I$(top_builddir)/src/compiler/nir \ @@ -165,7 +164,7 @@ anv_entrypoints.c : anv_entrypoints_gen.py $(vulkan_include_HEADERS) CLEANFILES = $(BUILT_SOURCES) libvulkan_intel_la_LIBADD = $(WAYLAND_LIBS) -lxcb -lxcb-dri3 \ - $(top_builddir)/src/isl/libisl.la \ + $(top_builddir)/src/intel/isl/libisl.la \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ ../mesa/libmesa.la \ ../mesa/drivers/dri/common/libdri_test_stubs.la \ diff --git a/src/vulkan/anv_private.h b/src/vulkan/anv_private.h index 06b961495c2..ba86333525e 100644 --- a/src/vulkan/anv_private.h +++ b/src/vulkan/anv_private.h @@ -62,7 +62,7 @@ typedef uint32_t xcb_window_t; #include "anv_entrypoints.h" #include "anv_gen_macros.h" #include "brw_context.h" -#include "isl.h" +#include "isl/isl.h" #ifdef __cplusplus extern "C" {