From: bugzilla-daemon Date: Tue, 12 May 2020 12:12:39 +0000 (+0000) Subject: [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47ba54c6fc5ffa821cc19aeb47b27864d8e2cc4f;p=libre-riscv-dev.git [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC --- diff --git a/b8/a16609b8a55d45e97155fa761d90fd7c14f6bb b/b8/a16609b8a55d45e97155fa761d90fd7c14f6bb new file mode 100644 index 0000000..96540a2 --- /dev/null +++ b/b8/a16609b8a55d45e97155fa761d90fd7c14f6bb @@ -0,0 +1,71 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Tue, 12 May 2020 13:12:41 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jYTm5-0002Fa-00; Tue, 12 May 2020 13:12:40 +0100 +Received: from localhost ([127.0.0.1] helo=bugs.libre-soc.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jYTm3-0002FI-BY + for libre-riscv-dev@lists.libre-riscv.org; Tue, 12 May 2020 13:12:39 +0100 +From: bugzilla-daemon@libre-soc.org +To: libre-riscv-dev@lists.libre-riscv.org +Date: Tue, 12 May 2020 12:12:39 +0000 +X-Bugzilla-Reason: CC +X-Bugzilla-Type: changed +X-Bugzilla-Watch-Reason: None +X-Bugzilla-Product: Libre-SOC's first SoC +X-Bugzilla-Component: Source Code +X-Bugzilla-Version: unspecified +X-Bugzilla-Keywords: +X-Bugzilla-Severity: enhancement +X-Bugzilla-Who: lkcl@lkcl.net +X-Bugzilla-Status: RESOLVED +X-Bugzilla-Resolution: DUPLICATE +X-Bugzilla-Priority: --- +X-Bugzilla-Assigned-To: yimmanuel3@gatech.edu +X-Bugzilla-Flags: +X-Bugzilla-Changed-Fields: bug_status resolution +Message-ID: +In-Reply-To: +References: +X-Bugzilla-URL: https://bugs.libre-soc.org/ +Auto-Submitted: auto-generated +MIME-Version: 1.0 +Subject: [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +aHR0cHM6Ly9idWdzLmxpYnJlLXNvYy5vcmcvc2hvd19idWcuY2dpP2lkPTMwMwoKTHVrZSBLZW5u +ZXRoIENhc3NvbiBMZWlnaHRvbiA8bGtjbEBsa2NsLm5ldD4gY2hhbmdlZDoKCiAgICAgICAgICAg +V2hhdCAgICB8UmVtb3ZlZCAgICAgICAgICAgICAgICAgICAgIHxBZGRlZAotLS0tLS0tLS0tLS0t +LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t +LS0tLS0tCiAgICAgICAgICAgICBTdGF0dXN8Q09ORklSTUVEICAgICAgICAgICAgICAgICAgIHxS +RVNPTFZFRAogICAgICAgICBSZXNvbHV0aW9ufC0tLSAgICAgICAgICAgICAgICAgICAgICAgICB8 +RFVQTElDQVRFCgotLS0gQ29tbWVudCAjMiBmcm9tIEx1a2UgS2VubmV0aCBDYXNzb24gTGVpZ2h0 +b24gPGxrY2xAbGtjbC5uZXQ+IC0tLQp3aG9vcHMgaG93IGRpZCB3ZSBlbmQgdXAgY3JlYXRpbmcg +MiBidWdyZXBvcnRzLCAjMzA0IGFuZCAjMzAzPwoKKioqIFRoaXMgYnVnIGhhcyBiZWVuIG1hcmtl +ZCBhcyBhIGR1cGxpY2F0ZSBvZiBidWcgMzA0ICoqKgoKLS0gCllvdSBhcmUgcmVjZWl2aW5nIHRo +aXMgbWFpbCBiZWNhdXNlOgpZb3UgYXJlIG9uIHRoZSBDQyBsaXN0IGZvciB0aGUgYnVnLgpfX19f +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaWJyZS1yaXNjdi1k +ZXYgbWFpbGluZyBsaXN0CmxpYnJlLXJpc2N2LWRldkBsaXN0cy5saWJyZS1yaXNjdi5vcmcKaHR0 +cDovL2xpc3RzLmxpYnJlLXJpc2N2Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpYnJlLXJpc2N2LWRl +dgo= +