From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Jun 2019 15:13:40 +0000 (+0100)
Subject: move add to its own simple example
X-Git-Tag: convert-csv-opcode-to-binary~4420
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47bf953e204b52cb16e5edfb66f648f388ad4149;p=libreriscv.git

move add to its own simple example
---

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 2143b8caf..63d912146 100644
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -243,6 +243,7 @@ See [[appendix]] for more details on fail-on-first modes.
 
 A greatly simplified example illustrating (just) the VL hardware for-loop
 is as follows:
+
 [[!inline raw="yes" pages="simple_v_extension/simple_add_example" ]]
 
 Note that zeroing, elwidth handling, SUBVL and PCVLIW have all been