From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jul 2019 12:47:50 +0000 (+0100)
Subject: workaround bug in use of ArrayProxy iteration / assignment
X-Git-Tag: ls180-24jan2020~943
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47c40840ff84bd7560bc26672119dd29d5e6a1c6;p=ieee754fpu.git

workaround bug in use of ArrayProxy iteration / assignment
---

diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index 0100880c..abe7dc94 100644
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -94,14 +94,12 @@ class FPPipeContext:
 
     def eq(self, i):
         ret = [self.muxid.eq(i.muxid)]
-        if self.op_wid:
-            ret.append(self.op.eq(i.op))
+        ret.append(self.op.eq(i.op))
         return ret
 
     def __iter__(self):
         yield self.muxid
-        if self.op_wid:
-            yield self.op
+        yield self.op
 
     def ports(self):
         return list(self)
diff --git a/src/ieee754/fpcommon/normtopack.py b/src/ieee754/fpcommon/normtopack.py
index 0f05795a..1cda8765 100644
--- a/src/ieee754/fpcommon/normtopack.py
+++ b/src/ieee754/fpcommon/normtopack.py
@@ -18,6 +18,7 @@ class FPNormToPack(FPState, SimpleHandshake):
 
     def __init__(self, width, pspec):
         FPState.__init__(self, "normalise_1")
+        print ("normtopack", pspec)
         self.pspec = pspec
         self.width = width
         SimpleHandshake.__init__(self, self) # pipeline is its own stage
diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index 7fe1a7c7..eae7c6b7 100644
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -12,13 +12,31 @@ from nmutil.singlepipe import Object
 from ieee754.fpcommon.getop import FPPipeContext
 
 
-class FPPackData(Object):
+class FPPackData:
 
     def __init__(self, width, pspec):
-        Object.__init__(self)
         self.z = Signal(width, reset_less=True)    # result
         self.ctx = FPPipeContext(width, pspec)
+
+        # this is complicated: it's a workaround, due to the
+        # array-indexing not working properly in nmigen.
+        # self.ports() is used to access the ArrayProxy objects by name,
+        # however it doesn't work recursively.  the workaround:
+        # drop the sub-objects into *this* scope and they can be
+        # accessed / set.  it's horrible.
         self.muxid = self.ctx.muxid
+        self.op = self.ctx.op
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.ctx.eq(i.ctx)]
+
+    def __iter__(self):
+        yield self.z
+        yield from self.ctx
+
+    def ports(self):
+        return list(self)
+
 
 class FPPackMod(Elaboratable):
 
diff --git a/src/nmutil/nmoperator.py b/src/nmutil/nmoperator.py
index 9a50f650..c035c37c 100644
--- a/src/nmutil/nmoperator.py
+++ b/src/nmutil/nmoperator.py
@@ -93,6 +93,7 @@ class Visitor2:
             yield from self.iterator2(ao.fields[field_name], val)
 
     def arrayproxy_iter2(self, ao, ai):
+        print ("arrayproxy_iter2", ai.ports(), ai, ao)
         for p in ai.ports():
             print ("arrayproxy - p", p, p.name, ao)
             op = getattr(ao, p.name)