From: lkcl <lkcl@web>
Date: Tue, 10 May 2022 15:19:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2274
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47db47c0207f7a21dad075e58c752b45c876f3c3;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 1fa821cbd..0a6b41971 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -490,16 +490,15 @@ The 32-bit on the other hand has four address rows, and so will take four write
 
 64-bit:
 
-* 0x00 - Configure GPIOs  0-7
-* 0x01 - Configure GPIOs  8-15
+* 0x00 - Configure GPIOs  0-7  - requires 8-bit `sel` one bit per GPIO
+* 0x01 - Configure GPIOs  8-15 - requires 8-bit `sel` one bit per GPIO
 
 32-bit:
 
-* 0x00 - Configure GPIOs  0-3
-* 0x01 - Configure GPIOs  4-7
-* 0x02 - Configure GPIOs  8-11
-* 0x03 - Configure GPIOs 12-15
-
+* 0x00 - Configure GPIOs  0-3 - requires 4-bit `sel` one bit per GPIO
+* 0x01 - Configure GPIOs  4-7 - requires 4-bit `sel` one bit per GPIO
+* 0x02 - Configure GPIOs  8-11 - requires 4-bit `sel` one bit per GPIO
+* 0x03 - Configure GPIOs 12-15 - requires 4-bit `sel` one bit per GPIO
 
 ## Combining JTAG BS Chain and Pinmux (In Progress)
 [[!img io_mux_bank_planning.JPG size="600x"]]