From: Jordan Justen Date: Tue, 15 Sep 2015 21:01:17 +0000 (-0700) Subject: i965/fs: The barrier send uses only 1 payload register X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47e18a595731c054ac254e26066e6dea804f34e8;p=mesa.git i965/fs: The barrier send uses only 1 payload register When preparing the barrier payload, the instructions should operate in simd8 mode since we only use 1 payload register. fs_inst::regs_read is also updated to indicate that it only reads one register for SHADER_OPCODE_BARRIER. These issues were flagged by: commit cadd7dd384b33a779d46bd664f456bed4a21a5b7 Author: Jason Ekstrand Date: Thu Jul 2 15:41:02 2015 -0700 i965/fs: Add a very basic validation pass Signed-off-by: Jordan Justen Reviewed-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 63bee0aa5fd..b4d05674260 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -797,6 +797,7 @@ fs_inst::regs_read(int arg) const break; case CS_OPCODE_CS_TERMINATE: + case SHADER_OPCODE_BARRIER: return 1; default: diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 8b61c867602..b85b52b38d8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1045,12 +1045,14 @@ fs_visitor::emit_barrier() fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); + const fs_builder pbld = bld.exec_all().group(8, 0); + /* Clear the message payload */ - bld.exec_all().MOV(payload, fs_reg(0u)); + pbld.MOV(payload, fs_reg(0u)); /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */ fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); - bld.exec_all().AND(component(payload, 2), r0_2, fs_reg(0x0f000000u)); + pbld.AND(component(payload, 2), r0_2, fs_reg(0x0f000000u)); /* Emit a gateway "barrier" message using the payload we set up, followed * by a wait instruction.