From: lkcl <lkcl@web>
Date: Mon, 24 Apr 2023 19:34:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=47f56c1181dd1ff5bc4ec114862640e6dd6c44f1;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 59e0e36fb..2b39ae9d7 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -1,5 +1,6 @@
 # setvl: Set Vector Length
 
+<!-- hide -->
 See links:
 
 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
@@ -11,6 +12,7 @@ See links:
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * [[sv/svstep]]
 * pseudocode [[openpower/isa/simplev]]
+<!-- show -->
 
 Add the following section to the Simple-V Chapter