From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 18 Aug 2020 00:34:15 +0000 (+0100)
Subject: add comment in dcache.py
X-Git-Tag: semi_working_ecp5~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=480b2348a2a08e518f355e25f62ffbedd51b3068;p=soc.git

add comment in dcache.py
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 3144ae1a..26d961a2 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -382,6 +382,10 @@ class Dcache(Elaboratable):
 #     signal dtlb_valids : tlb_valids_t;
 #     signal dtlb_tags : tlb_tags_t;
 #     signal dtlb_ptes : tlb_ptes_t;
+
+"""note: these are passed to nmigen.hdl.Memory as "attributes".  don't
+   know how, just that they are.
+"""
 #     attribute ram_style of dtlb_tags : signal is "distributed";
 #     attribute ram_style of dtlb_ptes : signal is "distributed";
         dtlb_valids = tlb_valids_t;